Zilog Z16C35 Instrukcja Użytkownika Pobierz pdf (Strona 272)

Application Note

Boost Your System Performance Using The Zilog ESCC

™

13-5

TRANSMIT FIFO INTERRUPT

In the ESCC, transmit interrupt frequencies are reduced by

a deeper Transmit FIFO and the revised transmit interrupt

structure. If the WR7' D5 Transmit FIFO Interrupt Level bit

is reset, the transmit interrupt is generated when the entry

location of the FIFO is empty, i.e., more data can be

written. This is downward compatible with a SCC Transmit

Interrupt since the SCC only has a one-byte transmit buffer

instead of a four-byte Transmit FIFO.

If WR7' D5 is set, the transmit buffer empty interrupt is

generated when the transmit FIFO is completely empty.

Enabling the transmit FIFO interrupt level, together with

polling the Transmit Buffer Empty (TBE) bit in RR0, causes

significant transmit interrupt frequency reduction. Transmit

data is sent in blocks of four bytes (algorithm is illustrated

in Figure 4). This helps to offload those systems which

have long interrupt latency or a fully loaded Operating

System.

Figure 4. Flowchart of Transmit Interrupt Service Routine to Reduce Transmit Interrupt Frequencies

Transmit FIFO

Full

Write Data To

Transmit FIFO

Is Loaded

With Data

TBE Interrupt

Service

RR0

TBE = '1'?

YES

TX FIFO Int.

Level Enabled

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Zilog Z16C35 Instrukcja Użytkownika Strona 272