Zilog Z16C35 Instrukcja Użytkownika Pobierz pdf (Strona 261)

Application Note

Using SCC with Z8000 in SDLC Protocol

12-6

INITIALIZATION

The SCC can be initialized for use in different modes by

setting various bits in its write registers. First, a hardware

reset must be performed by setting bits 7 and 6 of WR9 to

one; the rest of the bits are disabled by writing a logic zero.

SDLC protocol is established by selecting a SDLC mode,

sync mode enable, and a x1 clock in WR4. A data rate of

9600 baud, NRZ encoding, and a character length of eight

bits are among the other options that are selected in this

example (Table 2).

Note that WR9 is accessed twice, first to perform a

hardware reset and again at the end of the initialization

sequence to enable the interrupts. The programming

sequence depicted in Table 2 establishes the necessary

parameters for the receiver and transmitter so that they are

ready to perform communication tasks when enabled.

The Z8002 CPU must be operated in System mode to

execute privileged I/O instructions. So the Flag and

Control Word (FCW) should be loaded with system normal

(S//N), and the Vectored Interrupt Enable (VIE) bits set.

The Program Status Area Pointer (PSAP) is loaded with

address %4400 using the Load Control Instruction

(LDCTL). If the Z8000 Development Module is intended to

be used, the PSAP need not be loaded by the programmer

because the development module’s monitor loads it

automatically after the NMI button is pressed.

Since VIS and Status Low are selected in WR9, the

vectors listed in Table 3 will be returned during the

Interrupt Acknowledge cycle. Of the four interrupts listed,

only two, Ch A Receive Character Available and Ch A

Special Receive Condition, are used in the example given

here.

* Assuming that PSAP has been set to 4400 hex, “PS

Address” refers to the location in the Program Status Area

where the service routine address is stored for that

particular interrupt.

Table 2. Programming Sequence for Initialization

Value

(Hex) Effect

WR9 C0 Hardware reset

WR4 20 x1 clock, SDLC mode,

sync mode enable

WR10 80 NRZ, CRC preset to one

WR6 AB Any station address e.g. “AB”

WR7 7E SDLC ﬂag (01111110) = “7E”

WR2 20 Interrupt vector “20”

WR11 16 Tx clock from BRG output, /TRxC pin

= BRG out

WR12 CE Lower byte of time constant = “CE” for

9600 baud

WR13 0 Upper byte = 0

WR14 03 BRG source bit =1 for PCKL as input,

BRG enable

WR15 00 External Interrupt Disable

WR5 60 Transmit 8 bits/character SDLC CRC

WR3 C1 Rx 8 bits/character, Rx enable

(Automatic Hunt mode)

WR1 08 ext int. disable

WR9 09 MIE, VIS, status Low

Table 3. Interrupt Vectors

Vector PS Interrupt

(Hex) Address

28 446E Ch A Transmit Buffer Empty

2A 4472 Ch A External Status Change

2C 4476 Ch A Receive Char. Available

2E 447A Ch A Special Receive Condition

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