Zilog Z16C35 Instrukcja Użytkownika Pobierz pdf (Strona 236)

Application Note

SCC in Binary Synchronous Communications

10-6

INITIALIZATION

(Continued)

The Z8002 CPU must be operated in System mode in

order to execute privileged I/O instructions, so the Flag

Control Word (FCW) should be loaded with

System/Normal (S//N), and the Vectored Interrupt Enable

(VIE) bits set. The Program Status Area Pointer (PSAP) is

loaded with address %4400 using the Load Control

instruction (LDCTL). If the Z8000 Development Module is

intended to be used, the PSAP need not be loaded by the

programmer as the development modules monitor loads it

automatically after the NMI button is pressed.

Since VIS and Status Low are selected in WR9, the

vectors listed in Table 3 will be returned during the

Interrupt Acknowledge cycle. Of the four interrupts listed,

only two, Ch A Receive Character Available and Ch A

Special Receive Condition, are used in the example given

here.

* “PS Address” refers to the location in the Program Status

Area where the service routine address is stored for that

particular interrupt, assuming that PSAP has been set to

4400 hex.

Table 2. Programming Sequence for Initialization

Value

(hex) Effect

WR9 C0 Hardware reset

WR4 10 x1 clock, 16-bit sync,

sync mode enable

WR10 0 NRZ, CRC preset to zero

WR6 AB Any sync character “AB”

WR7 CD Any sync character “CD”

WR2 20 Interrupt vector “20”

WR11 16 Tx clock from BRG output,

TRxC pin = BRG out

WR12 CE Lower byte of time constant =

“CE” for 9600 baud

WR13 0 Upper byte = 0

WR14 03 BRG source bit = 1 for PCLK

as input, BRG enable

WR15 00 External interrupt disable

WR5 64 Tx 8 bits/character, CRC-16

WR3 C1 Rx8 bits/character, Rx enable

(Automatic Hunt mode)

WR1 08 RxInt on 1st char & sp. cond.,

ext. int. disable)

WR9 09 MIE, VIS, Status Low

Table 3. Interrupt Vectors

Vector

(hex)

Address*

(hex) Interrupt

28 446E Ch A Transmit Buffer Empty

2A 4472 Ch A External Status Change

2C 4476 Ch A Receive Char. Available

2E 447A Ch A Special Receive Condition

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