Zilog Z16C35 Instrukcja Użytkownika Pobierz pdf (Strona 179)

Application Note

The Z180™ Interfaced with the SCC at MHZ

7-2

INTERFACES

The following subsections explain the interfaces between

the:

■

Z180 and Memory

■

Z180 and I/O

■

Z180 and SCC

Basic goals of this system design are:

■

System clock up to 10 MHz

■

Using the Z8018010VSC (Z180 10 MHz PLCC

package) to take advantage of 1M byte addressing

space and compactness (DIP versions’ addressing

range is half; 512K bytes)

■

Using Z85C3010VSC (CMOS SCC 10 MHz PLCC

package)

■

Minimum parts count

■

Worst case design

■

Using EPLD for glue wherever possible

■

Expendability

The design method for EPLD is using TTLs (74HCT) and

then translating them into EPLD logic. This design uses

TTLs and EPLDs. With these goals in mind, the discussion

begins with the Z180-to-memory interface.

Z180 to Memory Interface

The memory access cycle timing of the Z180 is similar to

the Z80 CPU memory access cycle timing. The three

classifications are:

■

Opcode fetch cycle (Figure 1)

■

Memory read cycle (Figure 2)

■

Memory write cycle (Figure 3)

Table 1 shows the Z180’s basic timing elements for the

opcode’s fetch/memory read/write cycle.

Figure 1. Z180 Opcode Fetch Cycle Timing (One Wait State)

10 14

Addres

/MREQ

/RD

Data

/M1

Read Data

T1 T2 Tw T3 T1

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