Zilog Z16F2810 Instrukcja Użytkownika Strona 31

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UM018809-0611 Address Space
ZNEO
®
CPU Core
User Manual
15
Address Space
The ZNEO CPU has a unique memory architecture with a unified address space. It sup-
ports memory and I/O up to four buses:
Internal Non-Volatile Memory (Flash, EEPROM, EPROM, or ROM)
Internal RAM
Internal I/O Memory (internal peripherals)
External Memory (and/or memory-mapped peripherals)
The ZNEO CPU Fetch Unit and Execution Unit can access separate buses at the same
time. The CPU can access memories with either 8-bit or 16-bit bus widths. ZNEO CPU
uses 32-bit addressing internally. Therefore, the CPU is capable of addressing up to 4 GB
of addresses.
Current ZNEO CPU products ignore address bits [31:24], providing a 24-bit address space
with 16 MB (16,777,216 bytes) of unique memory addresses. Address bits [31:24] must
be written appropriately for the addressed space to allow for possible future expansion.
The CPU also provides instructions which use 16-bit addressing. 16-bit addresses are sign
extended by the CPU to access the highest and lowest 32 KB of the available address
space.
Example: The 16-bit address FEFFH resolves to FF_FEFFH in the 24-bit address space.
Most CPU instructions also use Arithmetic and Logic Unit (ALU) registers for either
source or destination data. See the ALU Registers
section on page 4.
The ZNEO CPU address space includes the following features:
Memory Map
Internal Nonvolatile Memory
Internal RAM
I/O Memory
External Memory
Endianness
Bus Widths
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