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UM018809-0611 Architectural Overview

ZNEO

CPU Core

User Manual

CPU Control Register (CPUCTL)

Bits [1:0] of the CPU Control Register (see Table 4 on page 13) control access to the

ZNEO CPU buses through DMA bandwidth selection.

For more details about the available peripheral control and data registers, and additional

information about DMA operation, refer to the device specific Product Specification.

Table 4. CPU Control Register

Bit 7 6 5 4 3 2 1 0

Field

Reserved DMABW

Reset

11111111

R/W

RRRRRRR/WR/W

Address

FFFF_E012H

Note: R = Read-only; R/W = Read/Write; R/W0 = Read/Write to 0.

Bit

Position Description

[7:2] Reserved; must be zero.

[1:0] DMA Bandwidth Selection (DMABW)

The ZNEO CPU can be configured to support four levels of Direct Memory Access (DMA) Con-

troller bus bandwidth. Write one of the following values to DMABW[1:0] to select the portion of

bus bandwidth allocated to DMA operations:

00 = DMA can consume 100% of the bus bandwidth

01 = DMA is allowed one transaction for each CPU operation

10 = DMA is allowed one transaction for every two CPU operations

11 = DMA is allowed one transaction for every three CPU operations

Note:

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 215 216

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