Zilog Z8F0130 Instrukcja Użytkownika

An CompanyCopyright © 2010 by Zilog®, Inc. All rights reserved.www.zilog.comZ8 Encore!® MicrocontrollerseZ8™ CPU CoreUser ManualUM012

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xManual ObjectivesThis user manual describes the architecture and instruction set of Zilog’s e

eZ8™ CPU CoreUser ManualUM012820-0810 ADDX Instruction85ADDX EE4h, B12hObject Code: 08 B1 2E E4If Register 46Ch contains the value 2Ah the following

eZ8™ CPU CoreUser ManualUM012820-0810 AND Instruction86ANDDefinitionLogical AND.SyntaxAND dst, srcOperationdst  dst AND src DescriptionThe source ope

eZ8™ CPU CoreUser ManualUM012820-0810 AND Instruction87Attributes Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 AND Instruction88AND R4, @R13Object Code: 53 4DIf Register 3Ah contains the value F5h (11110101b) and Register

eZ8™ CPU CoreUser ManualUM012820-0810 ANDX Instruction89ANDXDefinitionLogical AND using Extended Addressing.SyntaxANDX dst, srcOperationdst  dst AND

eZ8™ CPU CoreUser ManualUM012820-0810 ANDX Instruction90AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source

eZ8™ CPU CoreUser ManualUM012820-0810 ATM Instruction91ATMDefinitionAtomic Execution.SyntaxATMOperationThis new eZ8 instruction blocks all interrupt a

eZ8™ CPU CoreUser ManualUM012820-0810 ATM Instruction92AttributesMnemonicDestination, Source Byte 1 Byte 2 Byte 3 Byte 4ATM— 2F———

eZ8™ CPU CoreUser ManualUM012820-0810 BCLR Instruction93BCLRDefinitionBit Clear.SyntaxBCLR bit, dstOperationdst[bit]  0DescriptionFor this new eZ8 in

eZ8™ CPU CoreUser ManualUM012820-0810 BCLR Instruction94Sample UsageIf Working Register R7 contains the value 38h (00111000b), the follow-ing statemen

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xiAddress SpaceThis chapter describes the three address spaces accessible by the eZ8 CPU—Regis

eZ8™ CPU CoreUser ManualUM012820-0810 BIT Instruction95BITDefinitionBit Set/Reset.SyntaxBIT p, bit, dstOperationdst[bit]  pDescriptionFor his new eZ8

eZ8™ CPU CoreUser ManualUM012820-0810 BIT Instruction96Sample UsageIf Working Register R7 contains the value 38h (00111000b), the follow-ing statement

eZ8™ CPU CoreUser ManualUM012820-0810 BRK Instruction97BRKDefinitionOn-Chip Debugger Break.SyntaxBRKOperationNone.DescriptionThis new eZ8 instruction

eZ8™ CPU CoreUser ManualUM012820-0810 BSET Instruction98BSETDefinitionBit Set.SyntaxBSET bit, dstOperationdst[bit]  1DescriptionFor this new eZ8 inst

eZ8™ CPU CoreUser ManualUM012820-0810 BSET Instruction99Sample UsageIf Working Register R7 contains the value 38h (00111000b), the follow-ing statemen

eZ8™ CPU CoreUser ManualUM012820-0810 BSWAP Instruction100BSWAPDefinitionBit Swap.SyntaxBSWAP dstOperationdst[7:0]  dst[0:7]DescriptionFor this new e

eZ8™ CPU CoreUser ManualUM012820-0810 BSWAP Instruction101AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode R specifies a w

eZ8™ CPU CoreUser ManualUM012820-0810 BTJ Instruction102BTJDefinitionBit Test and Jump.SyntaxBTJ p, bit, src, DAOperationif src[bit] = p { PC  PC +

eZ8™ CPU CoreUser ManualUM012820-0810 BTJ Instruction103Flags0 4 100 0100 40 5 101 0101 50 6 110 0110 60 7 111 0111 71 0 000 1000 81 1 001 1001 91 2 0

eZ8™ CPU CoreUser ManualUM012820-0810 BTJ Instruction104AttributesSample UsageIf Working Register R7 contains the value 20h (00100000b), the BTJ instr

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xiiOp Codes Listed NumericallyThis chapter provides an easy reference for locating instruction

eZ8™ CPU CoreUser ManualUM012820-0810 BTJ Instruction105The next instruction executed after the BTJ is the LD instruction. The eZ8 CPU assembler autom

eZ8™ CPU CoreUser ManualUM012820-0810 BTJNZ Instruction106BTJNZDefinitionBit Test and Jump if Non-Zero.SyntaxBTJNZ bit, src, DAOperationif src[bit] =

eZ8™ CPU CoreUser ManualUM012820-0810 BTJNZ Instruction107FlagsAttributesSample UsageIf Working Register R7 contains the value 20h (00100000b), the BT

eZ8™ CPU CoreUser ManualUM012820-0810 BTJNZ Instruction108causes a Program Counter jump to occur because bit 5 of Working Regis-ter R7 passes the test

eZ8™ CPU CoreUser ManualUM012820-0810 BTJZ Instruction109BTJZDefinitionBit Test and Jump if Zero.SyntaxBTJZ bit, src, DAOperationif src[bit] = 0 { PC

eZ8™ CPU CoreUser ManualUM012820-0810 BTJZ Instruction110FlagsAttributesSample UsageIf Working Register R7 contains the value 20h (00100000b), the BTJ

eZ8™ CPU CoreUser ManualUM012820-0810 BTJZ Instruction111It causes a Program Counter jump to occur because bit 3 of Working Reg-ister R7 passes the te

eZ8™ CPU CoreUser ManualUM012820-0810 CALL Instruction112CALLDefinitionCALL procedure.SyntaxCALL dstOperationSP  SP – 2@SP  PCPC  dstDescriptionT

eZ8™ CPU CoreUser ManualUM012820-0810 CALL Instruction113AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode IR specifies a w

eZ8™ CPU CoreUser ManualUM012820-0810 CALL Instruction114CALL @A4hObject Code: D4 A4The Program Counter now points to the address of the first statem

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xiiiBracesThe curly braces, { }, indicate a single register or bus created by concate-nating s

eZ8™ CPU CoreUser ManualUM012820-0810 CCF Instruction115CCFDefinitionComplement Carry Flag.SyntaxCCFOperationC  ~CDescriptionThe Carry (C) flag is co

eZ8™ CPU CoreUser ManualUM012820-0810 CCF Instruction116Sample UsageIf the Carry flag contains a 0, the following statement sets the Carry flag to 1:C

eZ8™ CPU CoreUser ManualUM012820-0810 CLR Instruction117CLRDefinitionClearSyntaxCLR dstOperationdst  00hDescriptionThe destination operand is cleared

eZ8™ CPU CoreUser ManualUM012820-0810 CLR Instruction118Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a work

eZ8™ CPU CoreUser ManualUM012820-0810 COM Instruction119COMDefinitionComplement.SyntaxCOM dstOperationdst  ~dstDescriptionThe contents of the destina

eZ8™ CPU CoreUser ManualUM012820-0810 COM Instruction120Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a work

eZ8™ CPU CoreUser ManualUM012820-0810 CP Instruction121CPDefinitionCompare.SyntaxCP dst, srcOperationdst - srcDescriptionThe source operand is compare

eZ8™ CPU CoreUser ManualUM012820-0810 CP Instruction122Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify a work-ing

eZ8™ CPU CoreUser ManualUM012820-0810 CP Instruction123CP 34h,12hObject Code: A4 12 34If Register 4Bh contains the value 82h, Working Register R3 con

eZ8™ CPU CoreUser ManualUM012820-0810 CPC Instruction124CPCDefinitionCompare with Carry.SyntaxCPC dst, srcOperationdst - src - C DescriptionFor this n

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xivUse of the Terms LSB, MSB, lsb, and msbIn this document, the terms LSB and MSB, when appear

eZ8™ CPU CoreUser ManualUM012820-0810 CPC Instruction125AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can spec

eZ8™ CPU CoreUser ManualUM012820-0810 CPC Instruction126CPC R15, @R10Object Code: 1F A3 FAIf Register 34h contains the value 2Eh and Register 12h con

eZ8™ CPU CoreUser ManualUM012820-0810 CPCX Instruction127CPCXDefinitionCompare with Carry using Extended Addressing.SyntaxCPCX dst, srcOperationdst -

eZ8™ CPU CoreUser ManualUM012820-0810 CPCX Instruction128AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the sourc

eZ8™ CPU CoreUser ManualUM012820-0810 CPX Instruction129CPXDefinitionCompare using Extended Addressing.SyntaxCPX dst, srcOperationdst - srcDescription

eZ8™ CPU CoreUser ManualUM012820-0810 CPX Instruction130AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source

eZ8™ CPU CoreUser ManualUM012820-0810 DA Instruction131DADefinitionDecimal Adjust.SyntaxDA dstOperationdst  DA(dst) DescriptionThe destination operan

eZ8™ CPU CoreUser ManualUM012820-0810 DA Instruction132FlagsTable 24. Operation of the DAA Instruction InstructionCarry Before DABits 7–4 Value (Hex)H

eZ8™ CPU CoreUser ManualUM012820-0810 DA Instruction133AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can speci

eZ8™ CPU CoreUser ManualUM012820-0810 DA Instruction134Register 5Fh contains the value 42h and clears the C, Z, and S flags: V is undefined.0011 1100

eZ8™ CPU CoreUser ManualUM012820-0810 Manual Objectives xvAbbreviations/AcronymsThis document uses the following abbreviations or acronyms.Abbreviatio

eZ8™ CPU CoreUser ManualUM012820-0810 DEC Instruction135DECDefinitionDecrement.SyntaxDEC dstOperationdst  dst - 1DescriptionThe contents of the desti

eZ8™ CPU CoreUser ManualUM012820-0810 DEC Instruction136Attributes1Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can spe

eZ8™ CPU CoreUser ManualUM012820-0810 DECW Instruction137DECWDefinitionDecrement Word.SyntaxDECW dstOperationdst  dst - 1DescriptionThe 16-bit value

eZ8™ CPU CoreUser ManualUM012820-0810 DECW Instruction138AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes RR can specify

eZ8™ CPU CoreUser ManualUM012820-0810 DI Instruction139DIDefinitionDisable Interrupts.SyntaxDIOperationDisable Interrupts: IRQCTL[7]  0DescriptionBit

eZ8™ CPU CoreUser ManualUM012820-0810 DI Instruction140Sample UsageIf IRQCTL (Interrupt Control Register FCFh) contains 80h (10000000b), interrupts ar

eZ8™ CPU CoreUser ManualUM012820-0810 DJNZ Instruction141DJNZDefinitionDecrement and Jump if Non-Zero.SyntaxDJNZ dst, RAOperationdst  dst - 1if dst

eZ8™ CPU CoreUser ManualUM012820-0810 DJNZ Instruction142AttributesD UnaffectedH UnaffectedMnemonicDestination, AddressOp Code (Hex) Operand 1 Operand

eZ8™ CPU CoreUser ManualUM012820-0810 DJNZ Instruction143Sample UsageDJNZ typically controls a loop of instructions. In this example, 18 bytes are mov

eZ8™ CPU CoreUser ManualUM012820-0810 EI Instruction144EIDefinitionEnable Interrupts.SyntaxEIOperationEnable Interrupts: IRQCTL[7]  1DescriptionBit 7

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 1Architectural OverviewZilog’s eZ8™ CPU is the latest 8-bit central processing unit (CPU)

eZ8™ CPU CoreUser ManualUM012820-0810 EI Instruction145Sample UsageIf IRQCTL (Interrupt Control register FCFh) contains the value 00h (00000000b), int

eZ8™ CPU CoreUser ManualUM012820-0810 HALT Instruction146HALTDefinitionHalt mode.SyntaxHALTOperationHALT modeDescriptionThe HALT instruction places th

eZ8™ CPU CoreUser ManualUM012820-0810 HALT Instruction147Sample UsageThe following statement places the eZ8 CPU in HALT mode.HALTObject Code: 7F

eZ8™ CPU CoreUser ManualUM012820-0810 INC Instruction148INCDefinitionIncrement.SyntaxINC dstOperationdst  dst + 1DescriptionThe contents of the desti

eZ8™ CPU CoreUser ManualUM012820-0810 INC Instruction149Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a work

eZ8™ CPU CoreUser ManualUM012820-0810 INC Instruction150Sample UsageIf Working Register R10 contains the value 2Ah, the following statement leaves the

eZ8™ CPU CoreUser ManualUM012820-0810 INCW Instruction151INCWDefinitionIncrement Word.SyntaxINCW dstOperationdst  dst + 1 DescriptionThe 16-bit value

eZ8™ CPU CoreUser ManualUM012820-0810 INCW Instruction152AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes RR can specify

eZ8™ CPU CoreUser ManualUM012820-0810 IRET Instruction153IRETDefinitionInterrupt Return.SyntaxIRETOperationFLAGS  @SPSP  SP + 1PC  @SPSP  SP +

eZ8™ CPU CoreUser ManualUM012820-0810 IRET Instruction154AttributesSample UsageIf Stack Pointer High register, FFEh, contains the value EFh, Stack Poi

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 2Fetch UnitThe Fetch Unit controls the memory interface. Its primary function is to fetch

eZ8™ CPU CoreUser ManualUM012820-0810 JP Instruction155JPDefinitionJump.SyntaxJP dstOperationPC  dstDescriptionThe unconditional jump replaces the co

eZ8™ CPU CoreUser ManualUM012820-0810 JP Instruction156Attributes2Escaped Mode AddressingUsing Escaped Mode Addressing, address mode RR can specify a

eZ8™ CPU CoreUser ManualUM012820-0810 JP cc Instruction157JP CCDefinitionJump Conditionally.SyntaxJP cc, dstOperationif cc (condition code) is true (1

eZ8™ CPU CoreUser ManualUM012820-0810 JP cc Instruction158AttributesSample UsageIf the Carry flag is set, the following statement replaces the content

eZ8™ CPU CoreUser ManualUM012820-0810 JP cc Instruction159If the Carry flag is not set, control would have passed through to the state-ment following

eZ8™ CPU CoreUser ManualUM012820-0810 JR Instruction160JRDefinitionJump Relative.SyntaxJR DAOperationPC  PC + Xwhere the jump offset, X, is calculate

eZ8™ CPU CoreUser ManualUM012820-0810 JR Instruction161AttributesMnemonicCondition Code, AddressOp Code (Hex) Operand 1 Operand 2 Operand 3JR DA 8B X

eZ8™ CPU CoreUser ManualUM012820-0810 JR cc Instruction162JR CCDefinitionJump Relative Conditionally.SyntaxJR cc, DAOperationIf cc (condition code) is

eZ8™ CPU CoreUser ManualUM012820-0810 JR cc Instruction163AttributesMnemonicCondition Code, AddressOp Code (Hex) Operand 1 Operand 2 Operand 3JR F, DA

eZ8™ CPU CoreUser ManualUM012820-0810 LD Instruction164LDDefinitionLoad.SyntaxLD dst, srcOperationdst  srcDescriptionThe contents of the source opera

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 34. Present the Op Code and operands to the Instruction State Machine.The Fetch Unit is p

eZ8™ CPU CoreUser ManualUM012820-0810 LD Instruction165LD R1, IM E6 R1 IM —LD @R1, IM E7 R1 IM —LD @r1, r2 F3 {r1, r2} — —LD @R1, R2 F5 R2 R1 —LD r1,

eZ8™ CPU CoreUser ManualUM012820-0810 LD Instruction166Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a worki

eZ8™ CPU CoreUser ManualUM012820-0810 LD Instruction167If Working Register R13 contains the value 45h, and Working Register R12 contains the value 00h

eZ8™ CPU CoreUser ManualUM012820-0810 LD Instruction168The contents of Register 34h and Register 45h are not affected.If Working Register R0 contains

eZ8™ CPU CoreUser ManualUM012820-0810 LDC Instruction169LDCDefinitionLoad Constant to/from Program Memory.SyntaxLDC dst, srcOperationdst  srcDescript

eZ8™ CPU CoreUser ManualUM012820-0810 LDC Instruction170AttributesSample UsageIf Working Register Pair R6 and R7 contain the value 30A2h and Pro-gram

eZ8™ CPU CoreUser ManualUM012820-0810 LDCI Instruction171LDCIDefinitionLoad Constant to/from Program Memory and Auto-Increment Addresses.SyntaxLDCI ds

eZ8™ CPU CoreUser ManualUM012820-0810 LDCI Instruction172AttributesSample UsageIf Working Register Pair R6–R7 contains 30A2h, Program Memory loca-tion

eZ8™ CPU CoreUser ManualUM012820-0810 LDCI Instruction173A second instruction loads the value BCh into Program Memory location 30A3h:LDCI @RR6, @R2Ob

eZ8™ CPU CoreUser ManualUM012820-0810 LDE Instruction174LDEDefinitionLoad External Data to/from Data Memory.SyntaxLDE dst, srcOperationdst  srcDescri

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 4eZ8™ CPU Control RegistersThe eZ8 CPU contains four CPU control registers that are mappe

eZ8™ CPU CoreUser ManualUM012820-0810 LDE Instruction175Sample UsageIf Working Register Pair R6 and R7 contain the value 40A2h and Data Memory locatio

eZ8™ CPU CoreUser ManualUM012820-0810 LDEI Instruction176LDEIDefinitionLoad External Data to/from Data Memory and Auto-Increment Addresses.SyntaxLDEI

eZ8™ CPU CoreUser ManualUM012820-0810 LDEI Instruction177AttributesSample UsageIf Working Register Pair RR6 (R6 and R7) contains the value 404Ah, Data

eZ8™ CPU CoreUser ManualUM012820-0810 LDEI Instruction178LDEI @RR6, @R2Object Code: 93 26loads the value C3h into Data Memory location 404Bh. Working

eZ8™ CPU CoreUser ManualUM012820-0810 LDWX Instruction179LDWXDefinitionLoad Word using Extended Addressing.SyntaxLDWX dst, srcOperationdst  srcDescri

eZ8™ CPU CoreUser ManualUM012820-0810 LDWX Instruction180AttributesEscaped Mode AddressingAddress mode ER for the source or destination can specify a

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction181LDXDefinitionLoad using Extended Addressing.SyntaxLDX dst, srcOperationdst  src DescriptionFo

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction182AttributesEscaped Mode AddressingFor the LDX instruction, Escaped Mode Addressing for ER addre

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction183If the high byte of the source or destination address is EEh (11101110b), a working register i

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction184If Working Register R1 contains the value B3h, and Register 702h con-tains the value 46h, the

eZ8™ CPU CoreUser Manual UM012820-0810iiDO NOT USE IN LIFE SUPPORTLIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COM

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 5(256 byte boundary) of the Register File. The Stack Pointer Register val-ues are undefin

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction185The contents of Working Register Pair RR10, Register 0529h, and Regis-ter 0530h are not affect

eZ8™ CPU CoreUser ManualUM012820-0810 LDX Instruction186If Register Pair (20h, 21h) contains the value 0456h, and Register F2h contains the value BBh,

eZ8™ CPU CoreUser ManualUM012820-0810 LEA Instruction187LEADefinitionLoad Effective Address.SyntaxLEA dst, X(src)Operationdst  src + XDescriptionThis

eZ8™ CPU CoreUser ManualUM012820-0810 LEA Instruction188Sample UsageIf Working Register R3 contains the value 16h, the following statement leaves the

eZ8™ CPU CoreUser ManualUM012820-0810 MULT Instruction189MULTDefinitionMultiply.SyntaxMULT dstOperationdst[15:0]  dst[15:8] * dst[7:0]DescriptionThis

eZ8™ CPU CoreUser ManualUM012820-0810 MULT Instruction190Escaped Mode AddressingUsing Escaped Mode Addressing, address mode RR can specify a work-ing

eZ8™ CPU CoreUser ManualUM012820-0810 NOP Instruction191NOPDefinitionNo Operation.SyntaxNOPOperationNone.DescriptionNo action is performed by this ins

eZ8™ CPU CoreUser ManualUM012820-0810 OR Instruction192ORDefinitionLogical OR.SyntaxOR dst, srcOperationdst  dst OR src DescriptionThe source operand

eZ8™ CPU CoreUser ManualUM012820-0810 OR Instruction193AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can speci

eZ8™ CPU CoreUser ManualUM012820-0810 OR Instruction194(11111011b) in Working Register R4, sets the S flag, and clears the Z and V flags:OR R4, @R13O

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 6Interrupts, the Software Trap (TRAP) instruction, and Illegal Instruction Traps all writ

eZ8™ CPU CoreUser ManualUM012820-0810 ORX Instruction195ORX DefinitionLogical OR using Extended Addressing.SyntaxORX dst, srcOperationdst  dst OR src

eZ8™ CPU CoreUser ManualUM012820-0810 ORX Instruction196AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source

eZ8™ CPU CoreUser ManualUM012820-0810 POP Instruction197POPDefinitionPOP.SyntaxPOP dstOperationdst  @SPSP  SP + 1DescriptionExecution of the POP in

eZ8™ CPU CoreUser ManualUM012820-0810 POP Instruction198Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specifies a workin

eZ8™ CPU CoreUser ManualUM012820-0810 POPX Instruction199POPXDefinitionPOP using Extended Addressing.SyntaxPOPX dstOperationdst  @SPSP  SP + 1Descr

eZ8™ CPU CoreUser ManualUM012820-0810 POPX Instruction200AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER specifies a w

eZ8™ CPU CoreUser ManualUM012820-0810 PUSH Instruction201PUSHDefinitionPush.SyntaxPUSH srcOperationSP  SP - 1 @SP  srcDescriptionThe Stack Pointer

eZ8™ CPU CoreUser ManualUM012820-0810 PUSH Instruction202Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a wor

eZ8™ CPU CoreUser ManualUM012820-0810 PUSHX Instruction203PUSHXDefinitionPush using Extended Addressing.SyntaxPUSHX srcOperationSP  SP - 1 @SP  src

eZ8™ CPU CoreUser ManualUM012820-0810 PUSHX Instruction204AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER can specify

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 7Zero FlagFor arithmetic and logical operations, the Zero (Z) flag is 1 if the result is

eZ8™ CPU CoreUser ManualUM012820-0810 RCF Instruction205RCFDefinitionReset Carry Flag.SyntaxRCFOperationC  0DescriptionThe Carry (C) flag resets to 0

eZ8™ CPU CoreUser ManualUM012820-0810 RCF Instruction206Sample UsageIf the Carry flag is currently set, the following statement resets the Carry flag

eZ8™ CPU CoreUser ManualUM012820-0810 RET Instruction207RETDefinitionReturn.SyntaxRETOperationPC  @SPSP  SP + 2DescriptionThis instruction returns

eZ8™ CPU CoreUser ManualUM012820-0810 RET Instruction208AttributesSample UsageIf Stack Pointer contains the value 01A0h, register memory location 01A0

eZ8™ CPU CoreUser ManualUM012820-0810 RL Instruction209RLDefinitionRotate Left.SyntaxRL dstOperationDescriptionThe destination operand contents rotate

eZ8™ CPU CoreUser ManualUM012820-0810 RL Instruction210AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify a

eZ8™ CPU CoreUser ManualUM012820-0810 RLC Instruction211RLCDefinitionRotate Left through Carry.SyntaxRLC dstOperationDescriptionThe destination operan

eZ8™ CPU CoreUser ManualUM012820-0810 RLC Instruction212AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 RR Instruction213RRDefinitionRotate Right.SyntaxRR dstOperationDescriptionThe destination operand contents rotat

eZ8™ CPU CoreUser ManualUM012820-0810 RR Instruction214AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can speci

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 8of instruction that was last executed, enabling the subsequent decimal adjust (DA) opera

eZ8™ CPU CoreUser ManualUM012820-0810 RRC Instruction215RRCDefinitionRotate Right through Carry.SyntaxRRC dstOperationDescriptionThe destination opera

eZ8™ CPU CoreUser ManualUM012820-0810 RRC Instruction216AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 SBC Instruction217SBCDefinitionSubtract with Carry.SyntaxSBC dst, srcOperationdst  dst - src - C DescriptionThi

eZ8™ CPU CoreUser ManualUM012820-0810 SBC Instruction218AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can spec

eZ8™ CPU CoreUser ManualUM012820-0810 SBC Instruction219SBC R15, @R10Object Code: 33 FAIf Register 34h contains the value 2Eh, the Carry flag is set,

eZ8™ CPU CoreUser ManualUM012820-0810 SBCX Instruction220SBCXDefinitionSubtract with Carry using Extended Addressing.SyntaxSBCX dst, srcOperationdst 

eZ8™ CPU CoreUser ManualUM012820-0810 SBCX Instruction221AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the sourc

eZ8™ CPU CoreUser ManualUM012820-0810 SCF Instruction222SCFDefinitionSet Carry Flag.SyntaxSCFOperationC  1DescriptionThe Carry (C) flag is 1, regardl

eZ8™ CPU CoreUser ManualUM012820-0810 SCF Instruction223Sample UsageIf the Carry flag is currently reset, the following statement sets the Carry flag

eZ8™ CPU CoreUser ManualUM012820-0810 SRA Instruction224SRADefinitionShift Right Arithmetic.SyntaxSRA dstOperationDescriptionThis instruction performs

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 9Arithmetic Logic UnitThe Arithmetic Logic Unit (ALU) performs arithmetic and logical ope

eZ8™ CPU CoreUser ManualUM012820-0810 SRA Instruction225AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can spec

eZ8™ CPU CoreUser ManualUM012820-0810 SRL Instruction226SRLDefinitionShift Right Logical.SyntaxSRL dstOperationDescriptionFor this new eZ8 instruction

eZ8™ CPU CoreUser ManualUM012820-0810 SRL Instruction227AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 SRP Instruction228SRPDefinitionSet Register Pointer.SyntaxSRP srcOperationRP  srcDescriptionThe immediate value

eZ8™ CPU CoreUser ManualUM012820-0810 SRP Instruction229Attributes4Sample UsageThe following statement sets the Register Pointer to access Working Reg

eZ8™ CPU CoreUser ManualUM012820-0810 STOP Instruction230STOPDefinitionStop Mode.SyntaxSTOPOperationSTOP modeDescriptionThis instruction places the eZ

eZ8™ CPU CoreUser ManualUM012820-0810 STOP Instruction231Sample UsageThe following statements place the eZ8 CPU into STOP mode.STOPObject Code: 6F

eZ8™ CPU CoreUser ManualUM012820-0810 SUB Instruction232SUBDefinitionSubtract.SyntaxSUB dst, srcOperationdst  dst - src DescriptionThis instruction s

eZ8™ CPU CoreUser ManualUM012820-0810 SUB Instruction233AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 SUB Instruction234SUB R15, @R10Object Code: 23 FAThe D flag is set, and the C, Z, S, V, and H flags are cleared

eZ8™ CPU CoreUser ManualUM012820-0810 Architectural Overview 10Byte OrderingFor multibyte data, the eZ8 CPU stores the most significant byte in the lo

eZ8™ CPU CoreUser ManualUM012820-0810 SUBX Instruction235SUBXDefinitionSubtract using Extended Addressing.SyntaxSUBX dst, srcOperationdst  dst - srcD

eZ8™ CPU CoreUser ManualUM012820-0810 SUBX Instruction236AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the sourc

eZ8™ CPU CoreUser ManualUM012820-0810 SWAP Instruction237SWAPDefinitionSwap Nibbles.SyntaxSWAP dstOperationdst[7:4]  dst[3:0]DescriptionThis instruct

eZ8™ CPU CoreUser ManualUM012820-0810 SWAP Instruction238Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a wor

eZ8™ CPU CoreUser ManualUM012820-0810 TCM Instruction239TCMDefinitionTest Complement Under Mask.SyntaxTCM dst, srcOperation(NOT dst) AND srcDescriptio

eZ8™ CPU CoreUser ManualUM012820-0810 TCM Instruction240AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 TCM Instruction241ment resets the Z flag (because bit 3 in the destination operand is not a 1) and clears the V

eZ8™ CPU CoreUser ManualUM012820-0810 TCMX Instruction242TCMX DefinitionTest Complement Under Mask using Extended Addressing.SyntaxTCMX dst, srcOperat

eZ8™ CPU CoreUser ManualUM012820-0810 TCMX Instruction243AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the sourc

eZ8™ CPU CoreUser ManualUM012820-0810 TM Instruction244TMDefinitionTest Under Mask.SyntaxTM dst, srcOperationdst AND srcDescriptionThis instruction te

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 11Z8® CompatibilityThe eZ8™ CPU is an extension and improvement of Zilog’s popular, easy-to-us

eZ8™ CPU CoreUser ManualUM012820-0810 TM Instruction245AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify a

eZ8™ CPU CoreUser ManualUM012820-0810 TM Instruction246ment resets the Z flag (because bit 7 in the destination operand is not a 0), sets the S flag a

eZ8™ CPU CoreUser ManualUM012820-0810 TMX Instruction247TMX DefinitionTest Under Mask using Extended Addressing.SyntaxTMX dst, srcOperationdst AND src

eZ8™ CPU CoreUser ManualUM012820-0810 TMX Instruction248AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source

eZ8™ CPU CoreUser ManualUM012820-0810 TRAP Instruction249TRAPDefinitionSoftware Trap.SyntaxTRAP VectorOperationSP  SP - 2@SP  PCSP  SP - 1@SP 

eZ8™ CPU CoreUser ManualUM012820-0810 TRAP Instruction250FlagsAttributesSample UsageIf Register 68h contains the value A0h, and Register 69h contains

eZ8™ CPU CoreUser ManualUM012820-0810 WDT Instruction251WDTDefinitionWatchdog Timer Refresh.SyntaxWDTOperationNone.DescriptionEnable the Watchdog Time

eZ8™ CPU CoreUser ManualUM012820-0810 WDT Instruction252Sample UsageThe first execution of the following statement enables the Watchdog Timer:WDTObje

eZ8™ CPU CoreUser ManualUM012820-0810 XOR Instruction253XORDefinitionLogical Exclusive OR.SyntaxXOR dst, srcOperationdst  dst XOR srcDescriptionThe s

eZ8™ CPU CoreUser ManualUM012820-0810 XOR Instruction254AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR specify

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 12New Function InstructionsTable 3 lists the instructions that provide new functionality. Tabl

eZ8™ CPU CoreUser ManualUM012820-0810 XOR Instruction255(10010011b) in Working Register R4, sets the S flag, and clears the Z and V flags:XOR R4, @R13

eZ8™ CPU CoreUser ManualUM012820-0810 XORX Instruction256XORXDefinitionLogical Exclusive OR using Extended Addressing.SyntaxXORX dst, srcOperationdst

eZ8™ CPU CoreUser ManualUM012820-0810 XORX Instruction257AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the sourc

eZ8™ CPU CoreUser ManualUM012820-0810 Op Code Maps 258Op Code MapsFigure 19 displays Op Code map cell description and Table 25 provides the abbreviati

eZ8™ CPU CoreUser ManualUM012820-0810 Op Code Maps 259Table 25. Op Code Map Abbreviations Abbreviation Descriptionb Bit positioncc Condition codeX 8-b

eZ8™ CPU CoreUser ManualUM012820-0810 Op Code Maps 260Figure 20. First Op Code MapCP3.3R2,R1CP3.4IR2,R1CP2.3r1,r2CP2.4r1,Ir2CPX4.3ER2,ER1CPX4.3IM,ER1C

eZ8™ CPU CoreUser ManualUM012820-0810 Op Code Maps 261Figure 21. Second Op Code Map after 1FhCPC4.3R2,R1CPC4.4IR2,R1CPC3.3r1,r2CPC3.4r1,Ir2CPCX5.3ER2,

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 262Op Codes Listed NumericallyTable 26 lists the eZ8 CPU instructions, sorted numeri

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2630D JP F, dst DA –––––– 3 20E INC dst r – * * * – – 1 20F NOP –––––– 1 210 RLC dst

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2641F A3 CPC dst, src r Ir * * * * – – 3 41F A4 CPC dst, src R R * * * * – – 4 31F A

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 13Extended Addressing InstructionsNew Extended Addressing instructions allow data movement bet

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2652A DJNZ dst, RA r – – – – – – 2 Z/NZ3/42B JR LE, dst DA – – – – – – 2 22C LD dst,

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2663D JP ULE, dst DA – – – – – – 3 23E INC dst r – * * * – – 1 240 DA dst R * * * X

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 26753 AND dst, src r Ir – * * 0 – – 2 454 AND dst, src R R – * * 0 – – 3 355 AND dst

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 26867 TCM dst, src IR IM – * * 0 – – 3 468 TCMX dst, src ER ER – * * 0 – – 4 369 TCM

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2697A DJNZ dst, RA r – – – – – – 2 Z/NZ3/47B JR C, dst DA – – – – – – 2 27C LD dst,

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 2708D JP dst DA –––––– 3 28E INC dst r – * * * – – 1 28F DI –––––– 1 290 RL dst R *

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 271A1 INCW dst IRR – * * * – – 2 6A2 CP dst, src r r * * * * – – 2 3A3 CP dst, src r

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 272B5 XOR dst, src R IR – * * 0 – – 3 4B6 XOR dst, src R IM – * * 0 – – 3 3B7 XOR ds

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 273CA DJNZ dst, RA r – – – – – – 2 Z/NZ3/4CB JR NOV, dst DA – – – – – – 2 2CC LD dst

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 274DE INC dst r – * * * – – 1 2DF SCF 1––––– 1 2E0 RR dst R ****–– 2 2E1 RR dst IR *

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 14Alternate Function Op CodeTo accommodate the new instructions, the Op Code 1Fh refers to a n

eZ8™ CPU CoreUser ManualUM012820-0810 Op Codes Listed Numerically 275F2 TRAP Vector Vector–––––– 2 6F3 LD dst, src Ir r –––––– 2 3F4 MULT dst RR –––––

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 276Assembly and Object Code ExampleTable 27 provides an example listing file ou

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 27700101C 04 55 34 ADD %34, %5500101F 05 AA 35 ADD %35, @%AA001022 06 36 31 ADD

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 278001053 F6 27 FD BTJ 0, 2, r7, LABEL1001056 F6 B6 FA BTJ 1, 3, r6, LABEL10010

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 279001089 1F A2 57 CPC r5, r700108C 1F A3 68 CPC r6, @r800108F 1F A4 55 34 CPC

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 2800010C2 2A FA DJNZ r2, LABEL20010C4 3A F8 DJNZ r3, LABEL20010C6 4A F6 DJNZ r4

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 2810010E7 3E INC r30010E8 4E INC r40010E9 5E INC r50010EA 6E INC r60010EB 7E IN

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 282001107 3D F3 13 JP ULE, %F31300110A 4D F4 14 JP OV, %F41400110D 5D F5 15 JP

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 28300113E 7B 10 JR C, LABEL3001140 8B 0E JR T, LABEL3001142 9B 0C JR GE, LABEL3

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 284001166 BC 3B LD r11, #%3B001168 CC 3C LD r12, #%3C00116A DC 3D LD r13, #%3D

eZ8™ CPU CoreUser ManualUM012820-0810 Revision History iiiRevision HistoryEach instance in the Revision History reflects a change to this document fro

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 15continues to support these instructions. For more information, see the Addressing Modes on p

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 285001197 83 6A LDEI @r6, @rr10001199 93 3E LDEI @rr14, @r300119B C7 16 E3 LD r

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 2860011D3 43 68 OR r6, @r80011D5 44 55 34 OR %34, %550011D8 45 AA 35 OR %35, @%

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 287001205 C0 20 RRC %20001207 C1 46 RRC @%46001209 32 57 SBC r5, r700120b 33 68

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 288001239 26 36 31 SUB %36, #%3100123C 27 37 32 SUB @%37, #%3200123F 28 45 63 5

eZ8™ CPU CoreUser ManualUM012820-0810 Assembly and Object Code Example 289001277 79 35 03 64 TMX %364, #%3500127B F2 35 TRAP #%3500127D 5F WDT00127E B

eZ8™ CPU CoreUser ManualUM012820-0810 Index 290IndexSymbols# prefix 51% prefix 51@ prefix 51AADC instruction 53, 73ADCX instruction 53, 77addinstructi

eZ8™ CPU CoreUser ManualUM012820-0810 Index 291byte ordering 10CCALL procedure instruction 57, 112carry flag 6cc operand 50CCF instruction 6, 54, 55,

eZ8™ CPU CoreUser ManualUM012820-0810 Index 292instruction 57, 253using extended addressing 57, 256extended addressing register notation 50eZ8 CPUbloc

eZ8™ CPU CoreUser ManualUM012820-0810 Index 293CPU control 55load 55logical 56program control 57rotate and shift 58instruction set summary 58instructi

eZ8™ CPU CoreUser ManualUM012820-0810 Index 294203reset carry flag 54, 55, 205return 57, 205rotate left 58, 209rotate left with carry 58, 211rotate ri

eZ8™ CPU CoreUser ManualUM012820-0810 Z8® Compatibility 16Stack Pointer CompatibilityThe stack pointer is now 12 bits in length and provided by {SPH[3

eZ8™ CPU CoreUser ManualUM012820-0810 Index 295linear addressing 20loadconstant and auto-increment 54, 55, 171constant to/from program memory 55, 169e

eZ8™ CPU CoreUser ManualUM012820-0810 Index 296Pp operand 50page mode addressing 20PC symbol 51polarity notation 50polled interrupt processing 42POP i

eZ8™ CPU CoreUser ManualUM012820-0810 Index 297software trap 57, 249source operand symbol 51source program 47SP symbol 51SRA instruction 58, 224src sy

eZ8™ CPU CoreUser ManualUM012820-0810 Index 298notation 50pair notation 50XX symbol 51XOR instruction 57, 253XORX instruction 57, 256Zzero flag 7

eZ8™ CPU CoreUser ManualUM012820-0810 Customer Support 299Customer SupportFor answers to technical questions about the product, documentation, or any

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 17Address SpaceThe eZ8™ CPU can access three distinct address spaces:•The Register File contains a

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 18specific to your Z8 Encore! device to determine the number of registers available in the Registe

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 19Register Page using 4-bit addressing mode. Figure 3 on page 19 displays the organization of the

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 20Linear Addressing of Register FileUsing 12-bit linear addressing, the eZ8 CPU can directly acces

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 21Because Working Registers can be specified using fewer operand bytes, there are fewer bytes of c

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 22Bit AddressingMany eZ8 CPU instructions allow access to individual bits within regis-ters. Figur

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 23Register File PrecautionsSome control registers within the Register File provide Read-Only or Wr

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 24Individual products containing the eZ8 CPU support varying amounts of Program Memory. Refer to t

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents ivTable of ContentsManual Objectives. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 25StacksStack operations occur in the general-purpose registers of the Register File. The Register

eZ8™ CPU CoreUser ManualUM012820-0810 Address Space 26An overflow or underflow can occur when stack address is incremented or decremented beyond the a

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 38InterruptsInterrupt requests (IRQs) allow peripheral devices to suspend CPU operation and force the

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 39Interrupt PriorityThe Interrupt Controller prioritizes all interrupts. Refer to the Zilog Prod-uct

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 40Figure 17. Effects of an Interrupt on the StackTop of StackStack PointerFlags[7:0]PC[15:8]PC[7:0]St

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 41Figure 18. Interrupt Vectoring in Program Memory ExampleProgram MemoryVector Selected by Interrupt

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 42Nesting of Vectored InterruptsVectored interrupt nesting allows higher priority requests to interru

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 43JR Z, NEXT ; If no interrupt request, go ; to NEXT CALL SERVICE . If ; interrupt request, go to th

eZ8™ CPU CoreUser ManualUM012820-0810 Interrupts 44writes a 1 to bit 5 of Interrupt Request Register 1. If this interrupt at bit 5 is enabled and ther

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 27Addressing ModesThe eZ8™ CPU provides six addressing modes:•Register (R)•Indirect Register (I

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents vArchitectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 28Register AddressingExtended register addressing, symbol R, is used to directly access any reg

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 29Register Addressing Using 8-Bit AddressesRegisters or Register Pairs may be accessed using 8-

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 30within the current Working Register Group. This 4-bit address is com-bined with the Page Poin

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 31Escaped Mode Addressing with 8-bit AddressesUsing Escaped Mode Addressing 8-bit addresses can

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 32Indirect Register AddressingIn Indirect Register Addressing Mode, symbol IR, the contents of

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 33Figure 12. Indirect Register Addressing to Program or Data MemoryOne 8-bitProgram MemoryAddre

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 34Indexed AddressingAn Indexed Address, symbol X, consists of an 8-bit address in a working reg

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 35Direct AddressingFigure 14 displays the Direct Addressing mode, symbol DA. This instruc-tion

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 36Relative AddressingFigure 15 displays the Relative Addressing mode, symbol RA. The instructio

eZ8™ CPU CoreUser ManualUM012820-0810 Addressing Modes 37Immediate Data AddressingImmediate data, addressing symbol IM, is considered an addressing mo

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents viRegister File Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Regist

eZ8™ CPU CoreUser ManualUM012820-0810 Illegal Instruction Traps 45Illegal Instruction TrapsThe instruction set of the eZ8™ CPU does not cover all poss

eZ8™ CPU CoreUser ManualUM012820-0810 Illegal Instruction Traps 46Linear Programs That Do Not Employ The StackThe Stack Pointer must point to a sectio

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 47eZ8™ CPU Instruction Set SummaryeZ8 CPU assembly language enables writing to

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 48Assembly Language Source Program ExampleJP START ; Everything after the semic

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 49binary format must be followed if you prefer manual program coding or intend

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 50eZ8 CPU Instruction NotationIn the eZ8 CPU Instruction Summary and Descriptio

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 51Table 11 contains additional symbols that are used throughout the Instruc-tio

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 52An arrow (indicates assignment of a value. For example:dst  dst + srcindi

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 53Table 12. Arithmetic Instructions Mnemonic Operands InstructionADC dst, src A

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 54Table 13. Bit Manipulation Instructions Mnemonic Operands InstructionBCLR bit

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents viieZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52eZ8

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 55Table 15. CPU Control Instructions Mnemonic Operands InstructionATM – Atomic

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 56LDEI dst, src Load External Data to/from Data Memory and Auto-Increment Addre

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 57XOR dst, src Logical Exclusive ORXORX dst, src Logical Exclusive OR using Ext

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 58eZ8 CPU Instruction SummaryTable 20 summarizes the eZ8 CPU instructions. The

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 59Table 20. eZ8 CPU Instruction Summary AssemblyMnemonicSymbolic OperationAdd

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 60AND dst, src dst  dst AND src r r 52 – * * 0 – – 2 3rIr 53 2 4RR 54 3 3RIR 5

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 61BTJZ bit, src, dstif src[bit] = 0 PC  PC + Xr F6 –––––– 3 3Ir F7 3 4CALL

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 62CPC dst, srcdst – src – C r r 1F A2 ****–– 3 3rIr1F A3 3 4RR1F A4 4 3RIR1F A5

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 63EI Enable InterruptsIRQCTL[7]  19F –––––– 1 2HALT Halt Mode 7F –––––– 1 2IN

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 64LD dst, src dst  src r IM 0C–FC –––––– 2 2rX(r) C7 3 3X(r) r D7 3 4rIr E3 2

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents viiiHALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 65LDWX dst, srcdst  src ER ER 1FE8 –––––– 5 4LDX dst, src dst  src r ER 84 ––

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 66OR dst, src dst  dst OR src r r 42 – * * 0 – – 2 3rIr 43 2 4RR 44 3 3RIR 45

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 67RL dst R 90 ****–– 2 2IR 91 2 3RLC dst R 10 ****–– 2 2IR 11 2 3RR dst R E0 **

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 68SRA dst R D0 ***0–– 2 2IR D1 2 3SRL dst R 1F C0 * * 0 * – – 3 2IR 1F C1 3 3SR

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 69TCM dst, src (NOT dst) AND src r r 62 – * * 0 – – 2 3rIr 63 2 4RR 64 3 3RIR 6

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Summary 70XOR dst, src dst  dst XOR src r r B2 – * * 0 – – 2 3rIr B3 2 4RR B4 3 3RIR B

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Description 71eZ8™ CPU Instruction Set DescriptionThis chapter describes the assembly l

eZ8™ CPU CoreUser ManualUM012820-0810 eZ8™ CPU Instruction Set Description 72INSTRUCTION MNEMONICDefinitionDefinition of instruction mnemonic.SyntaxSi

eZ8™ CPU CoreUser ManualUM012820-0810 ADC Instruction73ADCDefinitionAdd with Carry.SyntaxADC dst, srcOperationdst  dst + src + CDescriptionThe source

eZ8™ CPU CoreUser ManualUM012820-0810 ADC Instruction74AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can speci

eZ8™ CPU CoreUser ManualUM012820-0810 Table of Contents ixSCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

eZ8™ CPU CoreUser ManualUM012820-0810 ADC Instruction75Example 2If Working Register R15 contains the value 16h, the Carry flag is not set, Working Reg

eZ8™ CPU CoreUser ManualUM012820-0810 ADC Instruction76Example 6If Register 6Ch contains the value 2Ah, and the Carry flag is not set, the following s

eZ8™ CPU CoreUser ManualUM012820-0810 ADCX Instruction77ADCXDefinitionAdd with Carry using Extended Addressing.SyntaxADCX dst, srcOperationdst  dst +

eZ8™ CPU CoreUser ManualUM012820-0810 ADCX Instruction78AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source

eZ8™ CPU CoreUser ManualUM012820-0810 ADCX Instruction79ADCX EE4h, B12hObject Code: 18 B1 2E E4If Register 46Ch contains the value 2Ah, and the Carry

eZ8™ CPU CoreUser ManualUM012820-0810 ADD Instruction80ADDDefinitionAddSyntaxADD dst, srcOperationdst  dst + srcDescriptionAdd the source operand to

eZ8™ CPU CoreUser ManualUM012820-0810 ADD Instruction81Escaped Mode AddressingUsing Escaped Mode Addressing, address modes R or IR can specify a worki

eZ8™ CPU CoreUser ManualUM012820-0810 ADD Instruction82If Register 34h contains the value 2Eh and Register 12h contains the value 1bh, the following s

eZ8™ CPU CoreUser ManualUM012820-0810 ADDX Instruction83ADDXDefinitionAdd using Extended Addressing.SyntaxADDX dst, srcOperationdst  dst + srcDescrip

eZ8™ CPU CoreUser ManualUM012820-0810 ADDX Instruction84AttributesEscaped Mode AddressingUsing Escaped Mode Addressing, address mode ER for the source