Zilog Z80180 Instrukcja Użytkownika Pobierz pdf (Strona 37)

100

101

Z8018x

Family MPU User Manual

UM005003-0703

Figure 12. Memory Read/Write (with Wait State) Timing Diagram

I/O Read/Write Timing

I/O Read/Write operations differ from memory Read/Write operations in

the following three ways:

•

The IORQ (I/O Request) signal is asserted Low instead of the MREQ

signal

•

The 16-bit I/O address is not translated by the MMU

•

A16–A19 are held Low

At least one Wait State (TW) is always inserted for I/O read and write

cycles (except internal I/O cycles).

Figure 13 illustrates I/O read/write timing with the automatically inserted

Wait State (TW).

T1 T1T2 TW T3 T2 T3

Phi

–

A19

–

MREQ

WAIT

Read Cycle

Write Cycle

Read data

Write data

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 325 326

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