
Z8018x
Family MPU User Manual
UM005003-0703
301
DMA/WAIT Control
Register:
DCNTL 3 2
Table 57. Internal I/O Registers (Continued)
Register Mnemonics Address Remarks
R/W R/W R/W R/W R/W R/W R/W R/W
11 11000
MWI1 MWI0 IWI1 DMS0
DIMA1
DIMA0IWI0
0
bit
during RESET
R/W
DMS1
The number of
0 0
MWI1,0
DMA Ch 1
I/O Memory
I/O Wait Insertion
Memory Wait Insertion
0
1
0 1
1 0
1 1
Mode Select
wait states
2
3
The number of
0 0
IWI1,0
0
2
0 1
1 0
1 1
wait states
3
4
1
DMSi
Edge sense
0
Sense
Level sense
0 0
DIM1,0
M
®I/O
0 1
1 0
1 1
Transfer Mode
M
®I/O
I/O
®
M
I/O
®
M
M
AR1+1
Address Increment/Decrement
M
AR1-1
I
AR1 fixed
I
AR1 fixed
I
AR1 fixed
I
AR1 fixed
M
AR1+1
M
AR1-1
DREQi Select, i=1,0
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