Zilog Z80180 Instrukcja Użytkownika Strona 149
- Strona / 326
- Spis treści
- BOOKMARKI
Oceniono. / 5. Na podstawie oceny klientów
Z8018x
Family MPU User Manual
134
UM005003-0703
pins are initialized as ASCI data clock inputs. If SS2, SS1 and SS0 are
reprogrammed (any other value than SS2, SS1, SS0 =
1) these pins
become ASCI data clock inputs. However, if DMAC channel 0 is
configured to perform memory to/from I/O (and memory mapped I/O)
transfers the CKA0/DREQ
0 pin reverts to DMA control signals
regardless of SS2, SS1, SS0 programming.
Also, if the CKA1D bit in the CNTLA register is
1, then the CKA1/
TEND
0 reverts to the DMA Control output function regardless of SS2,
SS1 and SS0 programming. Final data clock rates are based on CTS
/PS
(prescale), DR, SS2, SS1, SS0 and the Z8X180 system clock frequency
(Reference Table 19).
Each ASCI channel control register B configures multiprocessor mode,
parity and baud rate selection.
Table 18. Divide Ratio
SS2 SS1 SS0 Divide Ratio
000
¸ 1
001
¸ 2
010
¸ 4
011
¸ 8
100
¸ 16
101
¸ 32
110
¸ 64
1 1 1 external clock
- Family MPU 1
- MANUAL OBJECTIVES 3
- Intended Audience 3
- Manual Organization 3
- Sections 4
- Appendices 4
- Table of Contents 5
- List of Figures 8
- UM005003-0703 10
- List of Tables 12
- Status Signals 287 14
- FEATURES 16
- GENERAL DESCRIPTION 16
- PIN DESCRIPTION 22
- ARCHITECTURE 27
- OPERATION MODES 30
- 0 and IOC is 0 32
- CPU Timing 33
- Wait State Generator 42
- Bit 7 6 5 4 44
- MWI1 MWI0 MWI1 MWI0 44
- R/W R/W R/W R/W 44
- 1, selecting the 45
- Processors Only) 46
- SLP 2nd Op Code address 50
- Add-On Features 51
- STANDBY Mode 52
- IDLE Mode 55
- STANDBY-QUICK RECOVERY Mode 56
- Internal I/O Registers 56
- –0 Reserved ? ? Reserved 67
- Memory Management Unit (MMU) 69
- Figure 25. MMU Block Diagram 71
- 0 during I/O cycles 72
- MMU Register Description 75
- 0 during RESET 77
- 1 while all bits 78
- 0. The logical 64KB 78
- 0000H to FFFFH) 78
- Interrupts 80
- Interrupt Vector Low Register 81
- 00H during RESET 82
- N/A R/W R/W R/W 83
- 1 by the El (Enable 84
- 00000H was caused by 85
- INT0 Mode 0 90
- INT0 Mode 1 91
- INT0 Mode 2 93
- 00H and 94
- INT1, INT2 95
- 0. Each is also 96
- Family MPU User Manual 100
- Dynamic RAM Refresh Control 101
- TR1 TRW* TR2 102
- DMA Controller (DMAC) 105
- 107
- DMAC Register Description 108
- DMA Register Description 118
- Bits 5–3 119
- Bits 2–0 119
- DMA Operation 119
- Memory to Memory—Channel 0 120
- 00H) transfer 122
- Memory to ASCI - Channel 0 124
- Note: X = Don’t care 125
- T1 T2 T3 T3T2T1 130
- Processors 131
- ASCI Register Description 132
- 08H, 09H) 134
- 1) these pins 149
- 1, then the CKA1/ 149
- 0. Even after the 154
- Figure 56. ASCI Clock 156
- Baud Rate Generator 158
- CSI/O Block Diagram 161
- CSI/O Registers Description 162
- Address = 0BH) 164
- Interrupt Request 166
- = 0) when 167
- PRT Block Diagram 171
- PRT Register Description 172
- 0FH, CHI, 16H, 17H) 174
- Timer Control Register (TCR) 176
- PRT Interrupts 179
- PRT and RESET 179
- Secondary Bus Interface 180
- On-Chip Clock Generator 183
- Miscellaneous 187
- Software Architecture 188
- CPU REGISTERS 190
- Accumulator (A, A') 191
- Flag Registers (F, F') 192
- Interrupt Vector Register (I) 192
- R Counter (R) 192
- Index Registers (IX, and IY) 192
- Stack Pointer (SP) 193
- Program Counter (PC) 193
- Flag Register (F) 193
- Addressing Modes 195
- Implied Register (IMP) 195
- Register Direct (REG) 195
- Register Indirect (REG) 196
- Indexed (INDX) 197
- Extended (EXT) 197
- Immediate (IMMED) 198
- Relative (REL) 198
- IO (I/O) 199
- DC Characteristics 200
- Z80180 DC CHARACTERISTICS 201
- Z8S180 DC CHARACTERISTICS 202
- Z8L180 DC CHARACTERISTICS 204
- AC Characteristics 208
- Timing Diagrams 213
- STANDARD TEST CONDITIONS 221
- Instruction Set 223
- CONDITION 224
- RESTART ADDRESS 225
- MISCELLANEOUS 226
- DATA TRANSFER INSTRUCTIONS 238
- Special Control Instructions 251
- Instruction Summary 253
- Op Code Map 263
- DDH 22H : LD (mn), IX 264
- Bus Control Signal Conditions 267
- INTERRUPTS 295
- Operating Modes Summary 297
- REQUEST PRIORITY 298
- OPERATION MODE TRANSITION 299
- 0000H (all DMA transfers) 301
- Status Signals 303
- PIN STATUS 304
- –A17, A19 — Z 1 A 1 305
- –D7— ZZAZ 305
- INTERNAL I/O REGISTERS 309
- Ch 0 Destination Mode 1,0 315
- ORDERING INFORMATION 319
Powiązane produkty i podręczniki dla Czujniki Zilog Z80180
Czujniki Zilog Z86193 Instrukcja Użytkownika
(260 strony)
(260 strony)
Czujniki Zilog Z86C36 Instrukcja Użytkownika
(64 strony)
(64 strony)
Czujniki Zilog Z86E07 Instrukcja Użytkownika
(43 strony)
(43 strony)
Czujniki Zilog Z08470 Instrukcja Użytkownika
(326 strony)
(326 strony)
Czujniki Zilog Z08470 Instrukcja Użytkownika
(330 strony)
(330 strony)
Czujniki Zilog Z8PE002 Instrukcja Użytkownika
(48 strony)
(48 strony)
Czujniki Zilog Z8PE002 Instrukcja Użytkownika
(44 strony)
(44 strony)
Czujniki Zilog Z8FS021A Instrukcja Użytkownika
(25 strony)
(25 strony)
Czujniki Zilog ZEPIR0BA Instrukcja Użytkownika
(18 strony)
(18 strony)
Czujniki Zilog EZ80F91GA Instrukcja Użytkownika
(127 strony)
(127 strony)
Czujniki Zilog ZMOT0BHH Instrukcja Użytkownika
(34 strony)
(34 strony)
Czujniki Zilog Z16FMC2 Instrukcja Użytkownika
(26 strony)
(26 strony)
Czujniki Zilog ZAURA868 Instrukcja Użytkownika
(44 strony)
(44 strony)
Czujniki Zilog Z80230 Instrukcja Użytkownika
(394 strony)
(394 strony)
Czujniki Zilog ZAURCT Instrukcja Użytkownika
(59 strony)
(59 strony)
© 2020, manymanuals.pl. Wszelkie prawa zastrzeżone. | 0.073 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji