Zilog Z80180 Instrukcja Użytkownika Pobierz pdf (Strona 133)

Z8018x

Family MPU User Manual

118

UM005003-0703

When transmission is completed, the next byte (if available) is

automatically loaded from TDR into TSR and the next transmission

starts. If no data is available for transmission, TSR idles by outputting a

continuous High level. The TSR is not program-accessible.

ASCI Transmit Data Register 0, 1(TDR0,1:I/O Address = 06H, 07H)

Data written to the ASCI Transmit Data Register is transferred to the TSR

as soon as TSR is empty. Data can be written while TSR is shifting out the

previous byte of data. Thus, the ASCI transmitter is double buffered. Data

can be written into and read from the ASCI Transmit Data Register.

If data is read from the ASCI Transmit Data Register, the ASCI data

transmit operation is not affected by this read operation.

ASCI Transmit Data Register Ch. 0 (TDR0: 06H)

Bit 76543210

Bit/Field ASCI Transmit Channel 0

R/W R/W

Reset 0

Note: R = Read W = Write X = Indeterminate ? = Not Applicable

ASCI Transmit Data Register Ch. 1 (TDR1: 07H)

Bit 76543210

Bit/Field ASCI Transmit Channel 1

R/W R/W

Reset 0

Note: R = Read W = Write X = Indeterminate ? = Not Applicable

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Zilog Z80180 Instrukcja Użytkownika Strona 133