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SCC/ESCC
User Manual
UM010903-0515 Application Notes
267
Finally, an unpopulated 4-pin oscillator socket is included on the board with its output connected
to a single jumper/wire-wrap pin. This socket can be populated with a user-supplied oscillator and
connected to various clock pins among J5-J15.
Sensing Which Serial Controller Channel is Connected to the Console
To use the software provided with this evaluation board, one of the serial controller channels must
be connected to a PC or a dumb terminal via the J1 and J13 connectors. Some versions of this soft-
ware may restrict the choice to (E)SCC Channel A or (M)USC, depending on your application
needs. There is nothing in the hardware that limits the choice of which serial channel is used for
the console. However, on the J1-J4 (J13-J15) side, there are two things that are special about the
J1-J13 section as compared to the others. One is the provision for a Non-Maskable Interrupt in
response to a received Start bit, as described in addressing on page 257 .
Software can use the other special feature of the J1/J13 section, after a Reset, to sense which serial
channel is connected to the Console port. A Reset signal (from power-on or Reset button but not
from the Reset-The-ISCC, address decode (and others) described earlier) places the "NMI" EPLD
in a special mode where the first Start bit on the Consoles Transmit Data lead causes an NMI. This
feature can be used in a start-up procedure like the following example, to determine which serial
controller channel is used for the Console.
For each serial controller channel that the software can use for the Console:
1. Initialize the channel.
2. Send NULL character to the channel.
3. Wait for a short time to see if an NMI occurs. If an NMI occurs., the current channel is
the Console otherwise go on to the next serial channel and try again.
4 Port0 (Clock 0 In) Port0
5N/C N/C
6 Port3 (Rcv TSA Gate Out) Port3 (Rcv TSA Gate Out)
7 N/C (SYSCLK)
8 Port5 (Rcv Sync Out) Port5 (Rcv Sync Out)
9Port2 Port2
10 GND GND
11 PORT6 (Rcv Sync IN) PORT6 (Rcv Sync IN)
12 Port7 (Xmit Complete Out) Port7 (Xmit Complete Out)
Pin Assignments of Controller Port Connectors (Continued)
Pin No J11:IUSC Signal J12: (M)USC Signal
- SCC/ESCC 1
- UM010903-0515 2
- Revision History 3
- Table of Contents 4
- SCC’s Capabilities 9
- User Manual 13
- SCC Block Diagram 13
- Pin Descriptions 14
- Z85X30 DIP Pin Assignments 17
- Z85X30 PLCC Pin Assignments 18
- Z80X30 DIP Pin Assignments 19
- Interfacing the SCC/ESCC 24
- Z80X30 Write Cycle Timing 25
- Z80X30 Register Access 28
- Z80C30 Register Enhancement 31
- Z80230 Register Enhancements 32
- Z80X30 Reset 33
- Z85X30 Interface Timing 34
- Z85X30 Read Cycle Timing 35
- Z85X30 Write Cycle Timing 35
- D7-D0 Vector 36
- Z85X30 Register Access 37
- Z85C30 Register Enhancement 39
- Z85X30 Reset 41
- Interface Programming 42
- I/O Programming Introduction 43
- Interrupts 43
- External/Status Channel A 44
- Receive Channel B 44
- Transmit Channel B 44
- * Always 0 In B Channel 47
- Daisy-Chain Resolution 48
- Interrupt Acknowledge 51
- The Receiver Interrupt 52
- Receive Interrupts Disabled 53
- Conditio 56
- External/Status Interrupts 63
- Break/Abort 65
- Transmit Underrun/EOM 65
- CTS/DCD 66
- Zero Count 66
- Sync/Hunt 66
- Block/DMA Transfer 67
- SYNC Modes 68
- ASYNC Modes 68
- Wait On Receive 69
- DMA Requests 70
- DMA Request On Receive 74
- AD7-AD0 Receive DataWR8 75
- Test Functions 76
- Introduction 78
- Baud Rate Generator 78
- Data Encoding/Decoding 81
- Clock Selection 90
- Clock Multiplexer 92
- BRG Clock Source = /RTXC 93
- Crystal Oscillator 94
- Data Communication Modes 95
- Transmit Data Path 96
- Asynchronous Mode 99
- Asynchronous Transmit 100
- Asynchronous Receive 103
- Asynchronous Initialization 105
- Reg Bit No Description 107
- WR4 3 (=0) select sync mode 107
- State Changes in One 113
- /RTxC Clock Cycle 113
- SDLC Transmit 121
- SDLC Receive 127
- SDLC Frame Status FIFO 133
- Frame Status FIFO Circuitr 135
- Interface 135
- SDLC Loop Mode 137
- SDLC Loop Mode Receive 140
- SDLC Loop Mode Transmit 140
- Register Descriptions 143
- Write Registers 145
- Definition) 149
- Z85X30 Register Map 151
- Time Constant 175
- Clock Frequency 175
- Read Registers 181
- Read Register 1 185
- Read Register 2 187
- Read Register 3 188
- Read Register 8 191
- Read Register 10 192
- Read Register 12 193
- Read Register 13 194
- Read Register 15 194
- Application Notes 195
- Abstract 217
- Features 217
- Discussion 217
- Interfaces 218
- Z180 to Memory Interface 218
- EPROM Interface 220
- SRAM Interface 222
- SRAM Read Cycle 222
- SRAM Write Cycle 223
- Memory Interface Logic 223
- Physical Memory Address Map 225
- Z180 to I/O Interface 226
- Z180 I/O Write Cycle Timing 227
- Z180 to SCC Interface 230
- CPU Hardware Interfacing 230
- Data Bus Signals 230
- System Control Signals 230
- Interrupt Control 231
- SCC I/O Operation 231
- Read Cycle Timing 231
- Write Cycle Timing 232
- SCC Interrupt Operation 232
- Input/Output Cycles 234
- Z180 MPU to SCC Interface 234
- SCC I/O Read/Write Cycle 235
- I/O Read Cycle 235
- I/O Write Cycle 235
- Using EPLD 242
- System Checkout 243
- Software Considerations 244
- SCC Read Cycle Proof 244
- SCC Write Cycle Proof 244
- Interrupt Acknowledge Cycle 244
- (Continued) 246
- Summary 256
- General Description 257
- Processor 258
- Address Map 260
- (PBA)+511 269
- Serial Interfacing 270
- DMA channel 272
- Jumper Summary 276
- Control EPLD for 186 Board 278
- SCC EPLD for 186 Board 279
- DMA EPLD for 186 Board 280
- NMI Field for 186 Board 281
- Operation 295
- ESCC Controller 318
- Questions and Answers 382
- Customer Support 394
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