Zilog Z08470 Instrukcja Użytkownika Pobierz pdf (Strona 201)

UM008101-0601 Parallel Input/Output

System Clock (input). The Z80 PIO uses the standard Z80 system clock to

synchronize certain signals internally. This is a single phase clock.

Machine Cycle One Signal from CPU (input, active Low). This signal

from the CPU is used as a sync pulse to control several internal PIO opera-

tions. When M1

is active and the RD signal is active, the Z80 CPU is

fetching an instruction from memory. Conversely, when M1

is active and

IORQ is active, the CPU is acknowledging an interrupt. In addition, the M1

signal has two other functions within the Z80 PIO.

1. M1

synchronizes the PIO interrupt logic.

2. When M1

occurs without an active RD or IORQ signal, the PIO logic

enters a reset state.

IORQ

Input/Output Request from Z80 CPU (input,activeLow).TheIORQ

signal is used in conjunction with the B/ A Select, C/D Select, CE,and

RD signals to transfer commands and data between the Z80 CPU and the

Z80PIO.WhenCE,RD,andIORQare active, the port addressed by B/A

transfers data to the CPU (a read operation). Conversely, when CE

and

IORQ areactivebutRDis not active, then the port addressed by B/A is

written to from the CPU with either data or control information as speci-

fied by the C/D Select signal. Also, if IORQ and M1 are active simulta-

neously, the CPU is acknowledging an interrupt and the interrupting port

automatically places its interrupt vector on the CPU data bus if it is the

highest priority device requesting an interrupt.

Read Cycle Status from the Z80 CPU (input, active Low). If RD is active,

a MEMORY READ or I/O READ operation is in progress. The RD

signal

is used with B/A Select, C/D Select, CE

,andIORQsignals to transfer data

from the Z80 PIO to the Z80 CPU.

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Zilog Z08470 Instrukcja Użytkownika Strona 201