Zilog Z80180 Instrukcja Użytkownika Pobierz pdf (Strona 272)

100

101

Z8018x

Family MPU User Manual

256

UM005003-0703

DJNZ j

(If Br ¹ 0)

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 Ti*2 * Z 111 1 11 1

MC3 T1T2T3 1st operand

Address

j-2 010 1 11 1

MC4~M

TiTi * Z 1 1 1 1 1 1 1

DJNZ j

(If Br=0)

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 Ti*1 * Z 111 1 11 1

MC3 T1T2T3 1st operand

Address

j-2 010 1 11 1

EI*3 MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

EX DE, HL

EXX

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

EX AF, AF’

MC1 T1T2T3 1st Op Code

Address

1st

Op Code

010 1 01 0

MC2 Ti * Z 111 1 11 1

EX (SP), HL

MC1 T1T2T3 1st Op Code

Address

1st Op

Code

010 1 01 0

MC2 T1T2T3SP DATA 010 1 11 1

MC3 T1T2T3 SP+1 DATA 0 1 0 1 1 1 1

MC4 Ti * Z 111 1 11 1

MC5 T1T2T3 SP+1 H 1 0 0 1 1 1 1

MC6 T1T2T3SP L 100 1 11 1

*2 DMA,REFRESH, or BUS RELEASE cannot be executed after this state. (Request is ignored)

*3 Interrupt request is not sampled.

Table 51. Bus and Control Signal Condition in Each Machine Cycle (Continued)

Instruction

Machine

Cycle States Address Data RD WR MREQ IORQ M1 HALT ST

1 2 ... 267 268 269 270 271 272 273 274 275 276 277 ... 325 326

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