Zilog Z16C30 Instrukcja Użytkownika Pobierz pdf (Strona 24)

1-11

Z16C30 USC

®

USER'S MANUAL

ZILOG

UM97USC0100

Serial Clock

Logic

DPLL

Counters

BRG0, BRG1

Transmitter

Interrupt

Control

Interrupt

Control

Bus

Interface

Receive

FIFO

Receive

FIFO

Receiver

Receiver

Transmit

FIFO

DPLL

Counters

BRG0, BRG1

Serial Clock

Logic

Transmitter

Transmit

FIFO

Channel A

Channel B

16-Bit Internal

Data Bus

DMA

Controller,

System

Memory

Host

Processor

Figure 1-3. USC

®

Block Diagram

UM009402-0201

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 207 208

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