Zilog Z86193 Instrukcja Użytkownika

Copyright ©2008 by Zilog®, Inc. All rights reserved.www.zilog.comUM001604-0108User ManualZ8 Family of MicrocontrollersZ8® CPU

Z8® CPUUser ManualUM001604-0108 Z8® CPU Product Overview3Product Development SupportThe Z8® MCU product line is fully supported with a range of cros

Z8® CPUUser ManualUM001604-0108 Counters and Timers93Figure 87. Prescaler 1 Register ResetFigure 88. Prescaler 0 Reset U U U U U U

Z8® CPUUser ManualUM001604-0108 Counters and Timers94Figure 89. Timer Mode Register Reset 0 0 0 0 0 0 0 0 (% F1; Read/W

Z8® CPUUser ManualUM001604-0108 Interrupts95InterruptsZ8® CPU allows 6 different interrupts from a variety of sources; up to four external inputs, t

Z8® CPUUser ManualUM001604-0108 Interrupts96See the selected Z8 CPU's product specification for the exact interrupt sources supported.Interrupt

Z8® CPUUser ManualUM001604-0108 Interrupts97External Interrupt SourcesExternal sources involve interrupt request lines IRQ0–IRQ3. IRQ0, IRQ1, and IR

Z8® CPUUser ManualUM001604-0108 Interrupts98IRQ3 can be generated from an external source only if Serial In is not enabled. Otherwise, its source is

Z8® CPUUser ManualUM001604-0108 Interrupts99At sample time the request is transferred to the second flip-flop in Figure 94, that drives the interrup

Z8® CPUUser ManualUM001604-0108 Interrupts100Interrupt Priority Register InitializationThe Interrupt Priority Register (IPR) displayed in Figure 96

Z8® CPUUser ManualUM001604-0108 Interrupts101Interrupt Mask Register InitializationThe Interrupt Mask Register individually or globally enables or d

Z8® CPUUser ManualUM001604-0108 Interrupts102The RAM Protect option is selected at ROM mask submission time or at EPROM program time. If not selecte

Z8® CPUUser ManualUM001604-0108 Z8® CPU Product Overview4A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and provides an RS-232 cable

Z8® CPUUser ManualUM001604-0108 Interrupts103IRQ is always cleared to 00h and is read only until the first EI instruction, which enables the IRQ to

Z8® CPUUser ManualUM001604-0108 Interrupts104The proper sequence for programming the interrupt edge select bits is (assumes IPR and IMR have been pr

Z8® CPUUser ManualUM001604-0108 Interrupts105To generate a SWI, the appropriate request bit in the IRQ is set as follows:ORIRQ, #NUMBER where the im

Z8® CPUUser ManualUM001604-0108 Interrupts106Figure 100. Effects of an Interrupt on the StackSP Top of StackPC LOW BytePC HIGH ByteFLAGS

Z8® CPUUser ManualUM001604-0108 Interrupts107Vectored Interrupt Cycle TimingThe interrupt acknowledge cycle time is 24 internal clock cycles and is

Z8® CPUUser ManualUM001604-0108 Interrupts108longest instruction present in the application program + 2TPC (internal synchronization time).Nesting o

Z8® CPUUser ManualUM001604-0108 Interrupts109EI ;Enable interrupt mechanism DI ;Disable vectored interrupts.To initiate polled processing, check the

Z8® CPUUser ManualUM001604-0108 Power-Down Modes110Power-Down ModesIn addition to the standard RUN mode, the Z8® CPU supports two Power-Down modes t

Z8® CPUUser ManualUM001604-0108 Power-Down Modes111NOP instruction (opcode = FFh) immediately before the STOP instruction (opcode = 6Fh), that is,F

Z8® CPUUser ManualUM001604-0108 Power-Down Modes112Stop Mode Recovery RegisterThis register selects the clock divide value and determines the mode o

Z8® CPUUser ManualUM001604-0108 Address Space5Address SpaceIntroductionZ8® CPU includes the following four address spaces:•The Z8 Standard Register

Z8® CPUUser ManualUM001604-0108 Power-Down Modes113external clock frequency when this bit is set (D1 = 1). Using this bit together with D7 of PCON h

Z8® CPUUser ManualUM001604-0108 Power-Down Modes114If P31, P32, or P33 are to be used for a SMR source, the digital mode of operation must be select

Z8® CPUUser ManualUM001604-0108 Serial Input/Output115Serial Input/OutputUART IntroductionSome Z8® CPU microcontrollers contain an on-board full-dup

Z8® CPUUser ManualUM001604-0108 Serial Input/Output116UART Bit-Rate GenerationWhen Port 3 Mode Register bit 6 is set to 1, the UART is enabled and T

Z8® CPUUser ManualUM001604-0108 Serial Input/Output117To configure Z8® CPU for a specific bit rate, appropriate values as determined by the above eq

Z8® CPUUser ManualUM001604-0108 Serial Input/Output118The bit rate generator is started by setting the Timer Mode Register (TMR) (F1h) bit 1 and bit

Z8® CPUUser ManualUM001604-0108 Serial Input/Output119After a full character has been assembled in the receiver’s buffer, SIO Register (F0h), Interr

Z8® CPUUser ManualUM001604-0108 Serial Input/Output120Z8® CPU hardware supports odd parity only, that is enabled by setting the Port 3 Mode Register

Z8® CPUUser ManualUM001604-0108 Serial Input/Output121T0’s output drives a divide-by-16 counter that in turn generates a shift clock every 16 counts

Z8® CPUUser ManualUM001604-0108 Serial Input/Output122UART Reset ConditionsAfter a hardware reset, the SIO Register contents are undefined, and Seri

Z8® CPUUser ManualUM001604-0108 Address Space6Registers can be accessed as either 8-bit or 16-bit registers using Direct, Indirect, or Indexed Addre

Z8® CPUUser ManualUM001604-0108 Serial Input/Output123Mode Recovery, Master/Slave selection, and Compare mode. Table 25 contains the pin configurati

Z8® CPUUser ManualUM001604-0108 Serial Input/Output124If the associated IRQ3 is enabled, an interrupt is generated. Bit 5 controls the clock phase o

Z8® CPUUser ManualUM001604-0108 Serial Input/Output125SPI OperationThe SPI is used in one of two modes: either as system slave, or as system master.

Z8® CPUUser ManualUM001604-0108 Serial Input/Output126sion of the internal system clock if this is used as the SPI clock source. Divide by 2, 4, 8,

Z8® CPUUser ManualUM001604-0108 Serial Input/Output127slave modes. While in slave mode, if the RxBUF is not read before the next data stream is rece

Z8® CPUUser ManualUM001604-0108 Serial Input/Output128Figure 119. SPI LogicSPI Compare Register (SCOMP)SSD0DISKPortTCLKSMRBit ControlSPI ControlSPI

Z8® CPUUser ManualUM001604-0108 Serial Input/Output129Figure 120. SPI Data In/Out ConfigurationP27 OUTPINSPI ActiveP27 IN0 SOI D0 EnableOPEN-DRAINA

Z8® CPUUser ManualUM001604-0108 Serial Input/Output130Figure 121. SPI Clock/SPI Slave Select Output ConfigurationSPI MSTRPINP31+SPI ENP34SK INSPI

Z8® CPUUser ManualUM001604-0108 External Interface131External InterfaceIntroductionZ8® CPU can be a microcontroller with 20 pins for external memory

Z8® CPUUser ManualUM001604-0108 External Interface132Data Strobe (Output, Active Low)—Data Strobe (DS) provides the timing for data movement to or f

Z8® CPUUser ManualUM001604-0108 Address Space7When instructions are executed, registers are read when defined as sources and written when defined as

Z8® CPUUser ManualUM001604-0108 External Interface133Port 0 can be programmed to provide either four additional address lines (A11–A8), which increa

Z8® CPUUser ManualUM001604-0108 External Interface134Data MemoryThe two Z8 external memory spaces, data and program, are addressed as two separate s

Z8® CPUUser ManualUM001604-0108 External Interface135clock is shown for clarity only and does not have a specific timing relationship with other sig

Z8® CPUUser ManualUM001604-0108 External Interface136Address StrobeAll transactions start with AS driven Low and then raised High by Z8® CPU. The ri

Z8® CPUUser ManualUM001604-0108 External Interface137Extended Bus TimingSome products can accommodate slow memory access time by automatically inser

Z8® CPUUser ManualUM001604-0108 External Interface138Timing is extended by setting bit D5 in the Port 0–1 Mode Register (F8h) to 1 (see Figure 130).

Z8® CPUUser ManualUM001604-0108 External Interface139the current instruction, the opcode of the next instruction is fetched. Instruction pipelining

Z8® CPUUser ManualUM001604-0108 External Interface140Z8® Reset ConditionsAfter a hardware reset, extended timing is set to accommodate slow memory a

Z8® CPUUser ManualUM001604-0108 Instruction Set141Instruction SetZ8® instructions can be divided functionally into the following eight groups:•Load•

Z8® CPUUser ManualUM001604-0108 Instruction Set142INC dst IncrementINCW dst Increment WordSBC dst, src Subtract with CarrySUB dst, src SubtractTable

Z8® CPUUser ManualUM001604-0108 Address Space8With 4-bit addressing, the register file is logically divided into 16 Working Register Groups of 16 re

Z8® CPUUser ManualUM001604-0108 Instruction Set143Table 31. Block Transfer InstructionsMnemonic Operands InstructionLDCI dst, src Load Constant Auto

Z8® CPUUser ManualUM001604-0108 Instruction Set144Processor FlagsThe Flag Register (FCh) informs about the current status of Z8® CPU. The flags and

Z8® CPUUser ManualUM001604-0108 Instruction Set145Zero FlagFor arithmetic and logical operations, the Zero Flag (Z) is set to 1 if the result is zer

Z8® CPUUser ManualUM001604-0108 Instruction Set146IRET changes the value of the Decimal Adjust Flag when the Flag Register saved in the Stack is res

Z8® CPUUser ManualUM001604-0108 Instruction Set147Notation and Binary EncodingIn the detailed instruction descriptions that make up the rest of this

Z8® CPUUser ManualUM001604-0108 Instruction Set148Table 37. Notational ShorthandNotation Address Mode Operand Range *cc Condition Code See Condition

Z8® CPUUser ManualUM001604-0108 Instruction Set149Additional symbols used are listed in Table 38.Assignment of a value is indicated by the symbol “←

Z8® CPUUser ManualUM001604-0108 Instruction Set150In general, whenever an instruction format requires an 8-bit register address, that address can sp

Z8® CPUUser ManualUM001604-0108 Instruction Set151CP dst, srcdst − src† A[ ] [[[[––DA dst R 40 [[[X––dst ← DA dst IR 41DEC dst R 00 – [ [ [ – –dst

Z8® CPUUser ManualUM001604-0108 Instruction Set152JP cc, dst DA cD ––––––if cc is true, c = 0–Fthen PC ← dst IRR 30JR cc, dst RA cB ––––––if cc is

Z8® CPUUser ManualUM001604-0108 Address Space9Figure 4. Working Register Addressing Examples*Note: The full register file is shown. Refer to the sel

Z8® CPUUser ManualUM001604-0108 Instruction Set153dst ← src andr ← r + 1 orrr ←rr + 1lrr Ir 93NOP FF ––––––OR dst, srcdst ← dst OR src†4[ ]–[[0––POP

Z8® CPUUser ManualUM001604-0108 Instruction Set154SRP dstRP ← srcIm 31 ––––––STOP 6 F ––––––SUB dst, srcdst ← dst–src† 2[ ] [[[[1[SWAP dst RIRF0F1

Z8® CPUUser ManualUM001604-0108 Instruction Set155Table 40 provides a summary of Z8 address modes. Table 40. Summary of Z8® Address ModesAddress Mod

Z8® CPUUser ManualUM001604-0108 Instruction Set156Op Code MapFigure 134 displays the opcode map.Figure 134. Op Code Map 10.5CPR , R16.5DECR16.5DECI

Z8® CPUUser ManualUM001604-0108 Instruction Description157Instruction DescriptionTable 41 provides quick reference to each of the ZTP process manipu

Z8® CPUUser ManualUM001604-0108 Instruction Description158AddSyntax ADD dst, srcInstruction FormatOperationdst ← dst + srcThe source operand is adde

Z8® CPUUser ManualUM001604-0108 Instruction Description159Example 1If Working Register R3 contains 16h and Working Register R11 contains 20h, the st

Z8® CPUUser ManualUM001604-0108 Instruction Description160Example 6If Register D4h contains 5Fh and Register 5Fh contains 4Ch, the statement:ADD @D4

Z8® CPUUser ManualUM001604-0108 Instruction Description161Add With CarrySyntaxADC dst, srcInstruction FormatOperationdst ← dst + src + CThe source o

Z8® CPUUser ManualUM001604-0108 Instruction Description162Example 1If Working Register R3 contains 16h, the C Flag is set to 1, and Working Register

Z8® CPUUser ManualUM001604-0108 Address Space10Error ConditionsRegisters in the Z8® Standard Register File must be correctly used because certain co

Z8® CPUUser ManualUM001604-0108 Instruction Description163Example 6If Register D4h contains 5Fh, Register 5Fh contains 4Ch, and the C Flag is set, t

Z8® CPUUser ManualUM001604-0108 Instruction Description164Call ProcedureSyntaxCALL dstInstruction FormatOperationSP ← SP–2 @SP ← PC PC ← dstThe Stac

Z8® CPUUser ManualUM001604-0108 Instruction Description165Example 1If the contents of the PC are 1A47h and the contents of the SP (Registers FEh and

Z8® CPUUser ManualUM001604-0108 Instruction Description166Complement Carry FlagSyntaxCCFInstruction FormatOperationC ← NOT CThe C Flag is complement

Z8® CPUUser ManualUM001604-0108 Instruction Description167ClearSyntaxCLR dstInstruction FormatOperationdst ← 0The destination operand is cleared to

Z8® CPUUser ManualUM001604-0108 Instruction Description168ComplementSyntaxCOM dstInstruction FormatOperationdst ← NOT dstThe contents of the destina

Z8® CPUUser ManualUM001604-0108 Instruction Description169Example 2If Register 08h contains 24h, and Register 24h contains FFh (11111111b), the stat

Z8® CPUUser ManualUM001604-0108 Instruction Description170CompareSyntaxCP dst, srcInstruction FormatOperationdst–srcThe source operand is compared t

Z8® CPUUser ManualUM001604-0108 Instruction Description171If Working Register R3 contains 16h and Working Register R11 contains 20h, the state-ment:

Z8® CPUUser ManualUM001604-0108 Instruction Description172Decimal AdjustSyntaxDA dstInstruction FormatOperationdst ← DA dstThe destination operand i

Z8® CPUUser ManualUM001604-0108 Address Space11Currently, three out of the possible sixteen Z8 ERF Banks have been implemented. ERF Bank 0, also kno

Z8® CPUUser ManualUM001604-0108 Instruction Description173Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the

Z8® CPUUser ManualUM001604-0108 Instruction Description174 0011 1100 = 3Ch Register 45F contains the value 5Fh, and the result of the addition is s

Z8® CPUUser ManualUM001604-0108 Instruction Description175DecrementSyntaxDEC dstInstruction FormatOperationdst ← dst–1The contents of the destinatio

Z8® CPUUser ManualUM001604-0108 Instruction Description176Decrement and Jump if Non-ZeroSyntaxDJNZ r, dstInstruction FormatOperationr ← r–1; If r &l

Z8® CPUUser ManualUM001604-0108 Instruction Description177•End the loop with DJNZ The assembly listing required for this routine is as follows:

Z8® CPUUser ManualUM001604-0108 Instruction Description178Decrement WordSyntaxDECW dstInstruction FormatOperationdst ← dst–1The contents of the dest

Z8® CPUUser ManualUM001604-0108 Instruction Description179DECW @R0 Op Code: 81 E0leaves the value FAF2h in Register Pair 30h and 31h. The S Flag is

Z8® CPUUser ManualUM001604-0108 Instruction Description180Disable InterruptsSyntaxDlInstruction FormatOperationIMR (7) ← 0Bit 7 of Control Register

Z8® CPUUser ManualUM001604-0108 Instruction Description181Enable InterruptsSyntaxEIInstruction FormatOperationIMR (7) ← 0Bit 7 of Control Register F

Z8® CPUUser ManualUM001604-0108 Instruction Description182HaltSyntaxHALTInstruction FormatOperationThe HALT instruction turns off the internal CPU c

Z8® CPUUser ManualUM001604-0108 Address Space12When an ERF Bank is selected, register addresses 00h to 0Fh access those sixteen ERF Bank registers—i

Z8® CPUUser ManualUM001604-0108 Instruction Description183IncrementInstruction FormatOperationdst ← dst + 1The contents of the destination operand a

Z8® CPUUser ManualUM001604-0108 Instruction Description184Example 3If Register B3h contains CBh and Register BCh contains FFh, the statement:INC @B3

Z8® CPUUser ManualUM001604-0108 Instruction Description185Increment WordSyntaxINCW dstInstruction FormatOperationdst ← dst–1The contents of the dest

Z8® CPUUser ManualUM001604-0108 Instruction Description186Example 2If Working Register R0 contains 30h, and Register Pairs 30h and 31h contain the v

Z8® CPUUser ManualUM001604-0108 Instruction Description187Interrupt ReturnSyntaxIRETInstruction FormatOperationFLAGS ← @SP SP ← SP + 1 PC ← @SP SP ←

Z8® CPUUser ManualUM001604-0108 Instruction Description188JumpSyntaxJP cc, dstInstruction FormatOperationIf cc (condition code) is true, then PC ← d

Z8® CPUUser ManualUM001604-0108 Instruction Description189replaces the contents of the Program Counter with 1520h and transfers program control to t

Z8® CPUUser ManualUM001604-0108 Instruction Description190Jump RelativeSyntaxJR cc, dstInstruction FormatOperationIf cc is true, PC ← PC + dstIf the

Z8® CPUUser ManualUM001604-0108 Instruction Description191LoadSyntaxLD dst, srcInstruction FormatOperation dst ← srcThe contents of the source opera

Z8® CPUUser ManualUM001604-0108 Instruction Description192Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the

Z8® CPUUser ManualUM001604-0108 iiDO NOT USE IN LIFE SUPPORTLIFE SUPPORT POLICYZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENT

Z8® CPUUser ManualUM001604-0108 Address Space13The upper nibble of the register pointer selects which group of 16 bytes in the Register File, out of

Z8® CPUUser ManualUM001604-0108 Instruction Description193loads the value 00h into Register 45h. The contents of Working Register R12 and Work-ing R

Z8® CPUUser ManualUM001604-0108 Instruction Description194Example 11If Working Register R0 contains the value 08h and Register 2Ch (24h + 08h = 2Ch)

Z8® CPUUser ManualUM001604-0108 Instruction Description195Load ConstantSyntaxLDC dst, srcInstruction FormatOperationdst ← srcThis instruction is use

Z8® CPUUser ManualUM001604-0108 Instruction Description196loads the value 22h into Program Memory location 10A2h. The value of Working Regis-ter R2

Z8® CPUUser ManualUM001604-0108 Instruction Description197Load Constant AutoincrementSyntaxLDCI dst, srcInstruction FormatOperationdst ← src r ← r +

Z8® CPUUser ManualUM001604-0108 Instruction Description198LDCI @R2, @RR6 Op Code: C3 26loads the value BCh into Register 21h. Working Register Pair

Z8® CPUUser ManualUM001604-0108 Instruction Description199Load External DataSyntaxLDE dst, srcInstruction FormatOperationdst ← srcThis instruction i

Z8® CPUUser ManualUM001604-0108 Instruction Description200loads the value 22h into external data memory location 404AhThis instruction format is val

Z8® CPUUser ManualUM001604-0108 Instruction Description201Load External Data AutoincrementSyntaxLDEI dst, srcInstruction FormatOperationdst ← src r

Z8® CPUUser ManualUM001604-0108 Instruction Description202LDEI @R2, @RR6 Op Code: 83 26loads the value C3h into Register 23h. Working Register Pair

Z8® CPUUser ManualUM001604-0108 Address Space14Because enabling an ERF Bank (C or F) only changes register addresses 00h to 0Fh, the working registe

Z8® CPUUser ManualUM001604-0108 Instruction Description203No OperationSyntaxNOPInstruction FormatOperationNo action is performed by this instruction

Z8® CPUUser ManualUM001604-0108 Instruction Description204Logical ANDSyntaxAND dst, srcInstruction FormatOperationdst ← dst AND src The source opera

Z8® CPUUser ManualUM001604-0108 Instruction Description205Example 1If Working Register R1 contains 34h (00111000b) and Working Register R14 contains

Z8® CPUUser ManualUM001604-0108 Instruction Description206Example 6If Working Register R3 contains the value 3Eh and Register 3Eh contains the value

Z8® CPUUser ManualUM001604-0108 Instruction Description207Logical ORSyntaxOR dst, srcInstruction FormatOperationdst ← dst OR srcThe source operand i

Z8® CPUUser ManualUM001604-0108 Instruction Description208Example 1If Working Register R1 contains 34h (00111000b) and Working Register R14 contains

Z8® CPUUser ManualUM001604-0108 Instruction Description209Example 6 If Working Register R3 contains the value 3Eh and Register 3Eh contains the valu

Z8® CPUUser ManualUM001604-0108 Instruction Description210Logical Exclusive ORSyntaxXOR dst, srcInstruction FormatOperationdst ← dst XOR src The sou

Z8® CPUUser ManualUM001604-0108 Instruction Description211Example 1If Working Register R1 contains 34h (00111000b) and Working Register R14 contains

Z8® CPUUser ManualUM001604-0108 Instruction Description212Example 6If Working Register R3 contains the value 3Eh and Register 3Eh contains the value

Z8® CPUUser ManualUM001604-0108 Address Space15Refer to the specific product specification to determine the above registers are imple-mented.Z8® Con

Z8® CPUUser ManualUM001604-0108 Instruction Description213POPSyntaxPOP dstInstruction FormatOperationdst ← @SP SP ← SP + 1The contents of the locati

Z8® CPUUser ManualUM001604-0108 Instruction Description214Example 2 If the SP (Control Registers FEh and FFh) contains the value 1000h, external dat

Z8® CPUUser ManualUM001604-0108 Instruction Description215PUSHSyntaxPUSH srcInstruction FormatOperationSP ← SP–1 @SP ← srcThe contents of the SP (st

Z8® CPUUser ManualUM001604-0108 Instruction Description216Example 2If the SP contains 61h and Working Register R4 contains FCh, the statement:PUSH @

Z8® CPUUser ManualUM001604-0108 Instruction Description217Reset Carry FlagSyntaxRCFInstruction FormatOperationC ← 0The C Flag is reset to 0, regardl

Z8® CPUUser ManualUM001604-0108 Instruction Description218ReturnSyntaxRETInstruction FormatOperationPC ← @SP SP ← SP + 2This instruction is normally

Z8® CPUUser ManualUM001604-0108 Instruction Description219Rotate LeftSyntaxRL dstInstruction FormatOperationC ← dst(7) dst(0) ← dst(7) dst(1) ← dst(

Z8® CPUUser ManualUM001604-0108 Instruction Description220of the operand. For example, if Working Register R12 (CH) is the destination operand, then

Z8® CPUUser ManualUM001604-0108 Instruction Description221Rotate Left Through CarrySyntaxRLC dstInstruction FormatOperationC← dst(7) dst(0) ← C dst(

Z8® CPUUser ManualUM001604-0108 Instruction Description222of the operand. For example, if Working Register R12 (CH) is the destination operand, then

Z8® CPUUser ManualUM001604-0108 Address Space16•Program Control Flags (FLAGS)•Register Pointer (RP)•Stack Pointer High-Byte (SPH)•Stack Pointer Low-

Z8® CPUUser ManualUM001604-0108 Instruction Description223Rotate RightSyntaxRR dstInstruction FormatOperationC ← dst(0) dst(0) ← dst(1) dst(1) ← dst

Z8® CPUUser ManualUM001604-0108 Instruction Description224Example 1If the contents of Working Register R6 are 31h (00110001B), the statement:RR R6 O

Z8® CPUUser ManualUM001604-0108 Instruction Description225Rotate Right Through CarrySyntaxRRC dstInstruction FormatOperationC ← dst(0) dst(0) ← dst(

Z8® CPUUser ManualUM001604-0108 Instruction Description226of the operand. For example, if Working Register R12 (CH) is the destination operand, then

Z8® CPUUser ManualUM001604-0108 Instruction Description227Set Carry FlagSyntaxSRCInstruction FormatOperationC ← 1The C Flag is set to 1, regardless

Z8® CPUUser ManualUM001604-0108 Instruction Description228Set Register PointerSyntaxSRP srcInstruction FormatOperationRP ← srcThe specified value is

Z8® CPUUser ManualUM001604-0108 Instruction Description229When an Expanded Register Bank, other than Bank 0 is selected, access to the Z8® Stan-dard

Z8® CPUUser ManualUM001604-0108 Instruction Description230group of 16 registers. Registers F0h to FFh can be accessed as Working Registers R0 to R15

Z8® CPUUser ManualUM001604-0108 Instruction Description231Shift Right ArithmeticSyntaxSRA dstInstruction FormatOperationC ← dst(0) dst(0) ← dst(1) d

Z8® CPUUser ManualUM001604-0108 Instruction Description232the operand. For example, if Working Register R12 (CH) is the destination operand, then EC

Z8® CPUUser ManualUM001604-0108 Address Space17Working Register Group 0 in ERF Bank 0 consists of the registers for Z8® General-Pur-pose Registers a

Z8® CPUUser ManualUM001604-0108 Instruction Description233STOPSyntaxSTOPInstruction FormatOperationThis instruction turns OFF the internal system cl

Z8® CPUUser ManualUM001604-0108 Instruction Description234SubtractSyntaxSUB dst, srcInstruction FormatOperationdst ← dst–srcThe source operand is su

Z8® CPUUser ManualUM001604-0108 Instruction Description235Example 1If Working Register R3 contains 16h, and Working Register R11 contains 20h, the s

Z8® CPUUser ManualUM001604-0108 Instruction Description236Example 6 If Register D4h contains 5Fh, Register 5Fh contains 4Ch, the statement:SUB @D4h,

Z8® CPUUser ManualUM001604-0108 Instruction Description237Subtract With CarrySyntaxSBC dst, srcInstruction FormatOperationdst ← dst–src–CThe source

Z8® CPUUser ManualUM001604-0108 Instruction Description238Example 1If Working Register R3 contains 16h, the C Flag is set to 1, and Working Register

Z8® CPUUser ManualUM001604-0108 Instruction Description239leaves the value 27h in Register 6Ch. The D Flag is set, and the C, Z, S, V, and H Flags a

Z8® CPUUser ManualUM001604-0108 Instruction Description240Swap NibblesSyntaxSWAP dstInstruction FormatOperationdst(7-4) ↔ dst(3-0)The contents of th

Z8® CPUUser ManualUM001604-0108 Instruction Description241Example 2If Working Register R5 contains BCh and Register BCh contains B3h (10110011B), th

Z8® CPUUser ManualUM001604-0108 Instruction Description242Test Complement Under MaskSyntaxTCM dst, srcInstruction FormatOperation(NOT dst) AND srcTh

Z8® CPUUser ManualUM001604-0108 Address Space18Working Register Group 0 in ERF Bank F consists of the control registers for STOP mode, WDT, and port

Z8® CPUUser ManualUM001604-0108 Instruction Description243Example 1If Working Register R3 contains 45h (01000101b) and Working Register R7 contains

Z8® CPUUser ManualUM001604-0108 Instruction Description244tests bit 1 of the destination operand for 1. The Z Flag is set indicating bit 1 in the de

Z8® CPUUser ManualUM001604-0108 Instruction Description245Test Under MaskSyntaxTM dst, srcInstruction FormatOperationdst AND srcThis instruction tes

Z8® CPUUser ManualUM001604-0108 Instruction Description246Example 1If Working Register R3 contains 45h (01000101b) and Working Register R7 contains

Z8® CPUUser ManualUM001604-0108 Instruction Description247tests bit 1 of the destination operand for 0. The Z Flag is set indicating bit 1 in the de

Z8® CPUUser ManualUM001604-0108 Instruction Description248Watchdog TimerSyntaxWDTInstruction FormatOperationThe WDT is a retriggerable one shot time

Z8® CPUUser ManualUM001604-0108 Instruction Description249Watchdog Timer Enable During Halt ModeSyntaxWDhInstruction FormatOperationWhen this instru

Z8® CPUUser ManualUM001604-0108 Index250IndexAacknowledge 107Address Strobe 136Addressing 132ART 115BBit Rate 116Bit-Rate 116Bus Operation 134Bus Ti

Z8® CPUUser ManualUM001604-0108 Index251IRQ Software Interrupt Generation 104LLatency 107Logic and Timing 98MMask 101, 109Master/Slave 123Master/Sla

Z8® CPUUser ManualUM001604-0108 Index252VVectored 105Vectored Interrupt Cycle Timing 107Vectored Processing 105WWorst Case 107ZZ8 140Z8 Reset Condit

Z8® CPUUser ManualUM001604-0108 Address Space19Program Memory The first 12 bytes of Program Memory are reserved for the interrupt vectors, as displa

Z8® CPUUser ManualUM001604-0108 Customer Support253Customer SupportFor answers to technical questions about the product, documentation, or any other

Z8® CPUUser ManualUM001604-0108 Address Space20Z8® External MemoryZ8 CPU, in some cases, has the capability to access external Program Memory with t

Z8® CPUUser ManualUM001604-0108 Address Space21External Data MemoryThe Z8 CPU, in some cases, can address up to 60 KB of external data memory beginn

Z8® CPUUser ManualUM001604-0108 Address Space22Z8® StacksStack operations can occur in either the Z8 Standard Register File or external data mem-ory

Z8® CPUUser ManualUM001604-0108 Revision HistoryiiiRevision HistoryEach instance in Revision History reflects a change to this document from its pre

Z8® CPUUser ManualUM001604-0108 Address Space23Figure 11. Stack OperationsPCL Top of StackStack ContentsPCHPCLPCHFLAGSAfter anInterrupt CycleS

Z8® CPUUser ManualUM001604-0108 Clock24ClockZ8® CPU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock ci

Z8® CPUUser ManualUM001604-0108 Clock25SCLK ÷ TCLK Divide-By-16 SelectThe D0 bit of the SMR controls a divide-by-16 prescaler of SCLK ÷ TCLK. The pu

Z8® CPUUser ManualUM001604-0108 Clock26Oscillator ControlIn some cases, the Z8® CPU offers software control of the oscillator to select low EMI driv

Z8® CPUUser ManualUM001604-0108 Clock27Oscillator OperationThe Z8® CPU uses a Pierce oscillator with an internal feedback (see Figure 16). The advan

Z8® CPUUser ManualUM001604-0108 Clock28LayoutTraces connecting crystal, caps, and the Z8® CPU oscillator pins should be as short and wide as possibl

Z8® CPUUser ManualUM001604-0108 Clock29Crystals and ResonatorsCrystals and ceramic resonators, displayed in Figure 18 should have the characteristic

Z8® CPUUser ManualUM001604-0108 Clock30Depending on operation frequency, the oscillator may require the addition of capacitors C1 and C2 (displayed

Z8® CPUUser ManualUM001604-0108 Clock31In Figure 18 through Figure 20, Zilog® recommends that you connect the load capacitor ground trace directly t

Z8® CPUUser ManualUM001604-0108 Clock32Simple series capacitance is calculated using the following equation:Sample calculation for capacitance C1 an

Z8® CPUUser ManualUM001604-0108 Table of ContentsivTable of ContentsZ8® CPU Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z8® CPUUser ManualUM001604-0108 Reset33ResetThis section describes the Z8® CPU reset conditions, reset timing, and register initializa-tion procedur

Z8® CPUUser ManualUM001604-0108 Reset34Program execution starts 5 to 10 clock cycles after internal RESET has returned High. The initial instruction

Z8® CPUUser ManualUM001604-0108 Reset35After a reset, the first routine executed should be one that initializes the control registers to the require

Z8® CPUUser ManualUM001604-0108 Reset36Figure 23. Example of External Power-On Reset CircuitTable 13. ERF Bank 0 Reset Values at RESETRegister (Hex)

Z8® CPUUser ManualUM001604-0108 Reset37Table 15. Sample Expanded Register File Bank F Reset ValuesRegister (Hex) Register NameBitsComments7654321000

Z8® CPUUser ManualUM001604-0108 Reset38Figure 24. Example of Z8 Reset with RESET Pin, WDT, SMR, and POR 256 TpC 256 512 1024

Z8® CPUUser ManualUM001604-0108 Reset39Figure 25. Example of Z8 Reset with WDT, SMR, and POR5ms POR 5 ms 15 ms 25 ms 100 ms

Z8® CPUUser ManualUM001604-0108 Watchdog Timer40Watchdog TimerThe WDT is a retriggerable one-shot timer that resets the Z8® CPU if it reaches its te

Z8® CPUUser ManualUM001604-0108 Watchdog Timer41The WDTMR register is accessible only during the first 60 processor cycles from the exe-cution of th

Z8® CPUUser ManualUM001604-0108 Watchdog Timer42Bits 5, 6, and 7—These bits are reserved.VCC Voltage Comparator—An on-board voltage comparator check

Z8® CPUUser ManualUM001604-0108 Table of ContentsvInput/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z8® CPUUser ManualUM001604-0108 Input/Output Ports43Input/Output PortsZ8® CPU features up to 32 lines dedicated to input and output. These lines are

Z8® CPUUser ManualUM001604-0108 Input/Output Ports44Input and Output RegistersEach bit of Ports 0, 1, and 2, has an input register, an output regist

Z8® CPUUser ManualUM001604-0108 Input/Output Ports45General I/O ModePort 0 can be an 8-bit, bidirectional, CMOS or TTL compatible I/O port. These ei

Z8® CPUUser ManualUM001604-0108 Input/Output Ports46Figure 30. Port 0 Configuration with Open-Drain Capability, Autolatch, and Schmitt-TriggerOENPor

Z8® CPUUser ManualUM001604-0108 Input/Output Ports47Read/Write OperationsIn the nibble I/O Mode, Port 0 is accessed as general-purpose register P0 (

Z8® CPUUser ManualUM001604-0108 Input/Output Ports48DAV0 (P32) and RDY0 (P35) when Port 0 is an input port, or RDY0 (P32) and DAV0 (P35) when Port 0

Z8® CPUUser ManualUM001604-0108 Input/Output Ports49Figure 33. Port 0 Handshake OperationFigure 34. Port 1 Configuration with Open-Drain Capability,

Z8® CPUUser ManualUM001604-0108 Input/Output Ports50Read/Write OperationsIn byte input or byte output mode, the port is accessed as General-Purpose

Z8® CPUUser ManualUM001604-0108 Input/Output Ports51Using the Port 0–1 Mode Register, Port 1 is configured as an output port by setting bits D4 and

Z8® CPUUser ManualUM001604-0108 Input/Output Ports52Port 2Port 2 is a general-purpose port. Figure 29 on page 45 displays a block diagram of Port 2.

Z8® CPUUser ManualUM001604-0108 Table of ContentsviPrescaler Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z8® CPUUser ManualUM001604-0108 Input/Output Ports53Figure 39. Port 2 Configuration with Open-Drain Capability, Autolatch, and Schmitt-TriggerFigure

Z8® CPUUser ManualUM001604-0108 Input/Output Ports54Read/Write OperationsPort 2 is accessed as General-Purpose Register P2 (02h). Port 2 is written

Z8® CPUUser ManualUM001604-0108 Input/Output Ports55open-drain output, the data returned is the value forced on the output pin by the external syste

Z8® CPUUser ManualUM001604-0108 Input/Output Ports56Port 3General Port I/OPort 3 differs structurally from Ports 0, 1, and 2. Port 3 lines are fixed

Z8® CPUUser ManualUM001604-0108 Input/Output Ports57Figure 44. Port 3 Block DiagramInputBufferInputRegisterOutputBufferOutputRegisterOutputRegisterW

Z8® CPUUser ManualUM001604-0108 Input/Output Ports58Figure 45. Port 3 Configuration with Comparator, Autolatch, and Schmitt-TriggerP31 (AN1)R247 = P

Z8® CPUUser ManualUM001604-0108 Input/Output Ports59Figure 46. Port 3 Configuration with ComparatorPINP370 P34, P37 Standard Output1 P34, P37 Comp

Z8® CPUUser ManualUM001604-0108 Input/Output Ports60Figure 47. Port 3 Configuration with SPI and Comparator OutputsSPI MSTRPINP31+SPI ENP34SK INSP

Z8® CPUUser ManualUM001604-0108 Input/Output Ports61Read/Write OperationsPort 3 is accessed as a General-Purpose Register P3 (03h). Port 3 is writte

Z8® CPUUser ManualUM001604-0108 Input/Output Ports62Figure 49. Port 3 Mode Register ConfigurationTable 17. Port 3 Line Functions Function Line Signa

Z8® CPUUser ManualUM001604-0108 Table of ContentsviiSerial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Z8® CPUUser ManualUM001604-0108 Input/Output Ports63Port HandshakeWhen Ports 0, 1, and 2 are configured for handshake operation, a pair of lines fro

Z8® CPUUser ManualUM001604-0108 Input/Output Ports64the port is not protected and can be overwritten by the Z8 CPU during the handshake sequence. To

Z8® CPUUser ManualUM001604-0108 Input/Output Ports65In applications requiring a strobed signal instead of the interlocked handshake, Z8® CPU can sat

Z8® CPUUser ManualUM001604-0108 Input/Output Ports66I/O Port Reset ConditionsFull ResetAfter a hardware reset, WDT reset, or a POR, Port Mode Regist

Z8® CPUUser ManualUM001604-0108 Input/Output Ports67Because the types and amounts of I/O vary greatly among the Z8® CPU family devices, it is recomm

Z8® CPUUser ManualUM001604-0108 Input/Output Ports68Analog ComparatorsSelect Z8 devices include two independent on-chip analog comparators. See the

Z8® CPUUser ManualUM001604-0108 Input/Output Ports69Port 3 inputs must be in digital mode if Port 3 is a Stop Mode Recovery source. The analog compa

Z8® CPUUser ManualUM001604-0108 Input/Output Ports70Figure 59. Port Configuration of Comparator Inputs on P31, P32, and P33P31 (AN1)R247 = P3M+-IRQ2

Z8® CPUUser ManualUM001604-0108 Input/Output Ports71Comparator ProgrammingExample of enabling analog comparator mode.X = any binary numberExample of

Z8® CPUUser ManualUM001604-0108 Input/Output Ports72Comparator OperationAfter enabling the Analog Comparator mode, P33 becomes a common reference in

Z8® CPUUser ManualUM001604-0108 Z8® CPU Product Overview1Z8® CPU Product OverviewZilog’s Z8® microcontroller (MCU) product line continues to expand

Z8® CPUUser ManualUM001604-0108 Input/Output Ports73IIOFor CMOS voltage comparator inputs, the input offset current (IIO) is the leakage current of

Z8® CPUUser ManualUM001604-0108 Input/Output Ports74Other Z8 MCUs feature a Port Configuration Register (PCON) for which Port 0 and Port 1 can be co

Z8® CPUUser ManualUM001604-0108 Input/Output Ports75•Low EMI output drivers have resistance of 200 Ω (typical)•Low EMI Oscillator•All output drivers

Z8® CPUUser ManualUM001604-0108 Input/Output Ports76On CMOS OTP EPROM Z8® MCUs, the Port 3 inputs P31, P32, P33, and the XTAL 1 pin have only the in

Z8® CPUUser ManualUM001604-0108 Input/Output Ports77Z8® CMOS AutolatchesI/O port bits that are configurable as inputs are protected against open cir

Z8® CPUUser ManualUM001604-0108 Input/Output Ports78second occurs when the input is connected to the output of a device with tri-state capabil-ity.T

Z8® CPUUser ManualUM001604-0108 Input/Output Ports79Vil (max), pullup or pull-down resistances must be calculated using Ref = R/Rp. For best case ST

Z8® CPUUser ManualUM001604-0108 Counters and Timers80Counters and TimersZ8® CPU provides up to two 8-bit counter/timers, T0 and T1, each driven by i

Z8® CPUUser ManualUM001604-0108 Counters and Timers81(TIN) using P31. Port 3 line P36 can serve as a timer output (TOUT) through which T0, T1, or th

Z8® CPUUser ManualUM001604-0108 Counters and Timers82Figure 70. Prescaler 0 RegisterFigure 71. Prescaler 1 RegisterD7 D6 D5 D4 D3 D2 D1 D0(%F

Z8® CPUUser ManualUM001604-0108 Z8® CPU Product Overview2default WDT clock source is an internal RC circuit (isolated from the device clock source).

Z8® CPUUser ManualUM001604-0108 Counters and Timers83Counter/Timer OperationUnder software control, counter/timers are started and stopped via the T

Z8® CPUUser ManualUM001604-0108 Counters and Timers84The counter timers remain at rest as long as the Enable Count bits are 0. To enable count-ing,

Z8® CPUUser ManualUM001604-0108 Counters and Timers8582). When the Prescaler Counter reaches its end-of-count, the initial value is reloaded and cou

Z8® CPUUser ManualUM001604-0108 Counters and Timers86Minimum duration is achieved by loading 01h (1 prescaler output count), maximum dura-tion is ac

Z8® CPUUser ManualUM001604-0108 Counters and Timers87and bit 6 to 1 and 0, respectively. The counter/timer TOUT mode is turned off by setting TMR bi

Z8® CPUUser ManualUM001604-0108 Counters and Timers88TIN ModesThe Timer Mode Register TMR (F1h; see Figure 80 on page 89) is used in conjunction wit

Z8® CPUUser ManualUM001604-0108 Counters and Timers89It is suggested that P31 be configured as an input line by setting P3M Register bit 5 to 0, alt

Z8® CPUUser ManualUM001604-0108 Counters and Timers90Gated Internal Clock ModeThe TIN Gated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1

Z8® CPUUser ManualUM001604-0108 Counters and Timers91T1 is triggered counting continues until software resets the Enable Count bit. Interrupt reques

Z8® CPUUser ManualUM001604-0108 Counters and Timers92Reset ConditionsAfter a hardware reset, the counter/timers are disabled and the contents of the