Zilog Z86193 Instrukcja Użytkownika Pobierz pdf (Strona 112)

CPU

User Manual

UM001604-0108 Interrupts

105

To generate a SWI, the appropriate request bit in the IRQ is set as follows:

ORIRQ, #NUMBER

where the immediate data, NUMBER, has a 1 in the bit position corresponding to the

appropriate level of the SWI. For example, if an SWI is required on IRQ5, NUMBER

would have a 1 in bit 5:

OR IRQ, #00100000b

With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and

there are no higher priority pending requests, control is transferred to the service routine

pointed to by the IRQ5 vector.

Vectored Processing

Each Z8 interrupt level has its own vector. When an interrupt occurs, control passes to the

service routine pointed to by the interrupt’s vector location in Program Memory. The

sequence of events for vectored interrupts is as follows:

•

PUSH PC Low byte on stack

•

PUSH PC High byte on stack

•

PUSH FLAGS on stack

•

Fetch High byte of vector

•

Fetch Low byte of vector

•

Branch to service routine specified by vector

Figure 100 on page 106 and Figure 101 on page 107 display the vectored interrupt opera-

tion.

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