Zilog Z08470 Instrukcja Użytkownika Pobierz pdf (Strona 184)

100

101

Z80 Instruction Set UM008007-0715

172

Z80 CPU

User Manual

Condition Bits Affected

S is set if most-significant bit of the Accumulator is 1 after an operation; otherwise, it is

reset.

Z is set if the Accumulator is 0 after an operation; otherwise, it is reset.

H: see the DAA instruction table on the previous page.

P/V is set if the Accumulator is at even parity after an operation; otherwise, it is reset.

N is not affected.

C: see the DAA instruction table on the previous page.

Example

An addition operation is performed between 15 (BCD) and 27 (BCD); simple decimal

arithmetic provides the following result:

The binary representations are added in the Accumulator according to standard binary

arithmetic, as follows:

0001 0101

+ 0010

0111

0011 1100 = 3C

The sum is ambiguous. The DAA instruction adjusts this result so that the correct BCD

representation is obtained, as follows:

0011 1100

+ 0000

0110

0100 0010 = 42

M Cycles T States 4 MHz E.T.

141.00

1 2 ... 179 180 181 182 183 184 185 186 187 188 189 ... 325 326

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