Zilog EZ80L92 Instrukcja Użytkownika Pobierz pdf (Strona 17)

eZ80L92 Development Kit

User Manual

UM012913-0407 Operational Description

16 GND

17 A2 Bidirectional Yes

18 A1 Bidirectional Yes

19 A11 Bidirectional Yes

20 A12 Bidirectional Yes

21 A4 Bidirectional Yes

22 A20 Bidirectional Yes

23 A5 Bidirectional Yes

24 A17 Bidirectional Yes

25 DIS_ETH

Output Low No

26 EN_FLASH

Output Low No

27 A21 Bidirectional Yes

28 V

29 A22 Bidirectional Yes

30 A23 Bidirectional Yes

Table 2. eZ80Acclaim!

Development Platform Peripheral Bus Connector

Identification—JP1

(Continued)

Pin No. Symbol Signal Direction Active Level eZ80L92 Signal

Notes:

1. For the sake of simplicity in describing the interface, Power and Ground nets are omitted from

this table. The entire interface is represented in the eZ80L92 Module Schematics. see

eZ80L92 Module.

2. The Power and Ground nets are connected directly to the eZ80L92 device.

Additional note: external capacitive loads on RD

, WR, IORQ, MREQ, D0–D7 and A0–A23 should be

below 10 pF to satisfy the timing requirements for the eZ80

CPU. All unused inputs should be

pulled to either V

or GND, depending on their inactive levels to reduce power consumption and

to reduce noise sensitivity. To prevent EMI, the EZ80CLK output can be deactivated via software in

the eZ80L92’s Peripheral Power-Down Register.

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 85 86

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